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PDF IP2022 Data sheet ( Hoja de datos )
| Número de pieza | IP2022 | |
| Descripción | (IP2012 / IP2022) Wireless Network Processor | |
| Fabricantes | Ubicom | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP2022 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
PRELIMINARY
March 17, 2003
IP2012 / IP2022 Wireless Network Processors
Features and Performance Optimized for Network Connectivity
1.0 Product Highlights
The Ubicom IP2012™ and IP2022™ Wireless Network
Processors combine support for communication physical
layer, Internet protocol stack, device-specific application,
and device-specific peripheral software modules in a
single chip, and are reconfigurable over the Internet. They
can be programmed, and reprogrammed, using pre-built
software modules and configuration tools to create true
single-chip solutions for a wide range of device-to-device
and device-to-human communication applications. High
speed communication interfaces are available via on-chip
hardware Serializer/Deserializer (SerDes) blocks. These
full-duplex blocks allow the IP2022 or IP2012 to be used
in a variety of communication bridging applications. Each
SerDes block is capable of supporting 10Base-T Ethernet
(MAC and PHY), USB, GPSI, SPI, or UART. The high-
speed operating frequency, combined with most
instructions executing in a single cycle, delivers the
throughput needed for emerging network connectivity
applications. A flash-based program memory allows both
in-system and runtime reprogramming. The IP2022 and
IP2012 implement most peripheral, communications and
control functions via software modules (ipModule™
software), replacing traditional hardware for maximum
system design flexibility. This approach allows rapid,
inexpensive product design and, when needed, quick and
easy reconfiguration to accommodate changes in market
needs or industry standards.
Key Features:
• Designed to support single-chip networked solutions
• Fast processor core
• 64kB Flash program memory
• 16kB SRAM data/program memory
• 4kB SRAM data memory
• Two SerDes communication blocks supporting com-
mon PHYs (Ethernet, USB, UARTs, etc.) and bridging
applications (IP2012 has only one SerDes unit)
• Advanced RISC processors
• IP2022 — 120 and 160 MHz versions
• IP2012 — 120 MHz version
• High speed packet processing
• Instruction set optimized for communication functions
• Supports software implementation of traditional hard-
ware functions
• In-system reprogrammable for highest flexibility
• Run time self-programmable
• Vpp = Vcc supply voltage
Choices for
Communication:
Host Bus
Customer Application
HTTP/SMTP/TFTP
TCP/UDP
IP/ICMP
Network Access Layer
PHY Firmware
IP2022/IP2012
ipOS Operating System
8/16-Bit Internet 64-Kbyte 16-Kbyte 4-Kbyte External General
Parallel Processor Flash Inst./Data Data Memory Purpose
Slave Port CPU Memory RAM
RAM Interface I/O Ports
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
Bluetooth HCI
High-Speed
Serial Unit 1
(SERDES)
5
Timers
PLL
Clock
Multiplier
8-Input
10-Bit
A/DC
ISP/ISD
Interface
High-Speed
Serial Unit 2
(SERDES)
Not available on IP2012
515-063b.eps
Choices for
Communication:
ISA (802.11b)
Mini-PCI/Cardbus
(802.11g/802.11a)
I2C
General-Purpose I/O
10Base-T Ethernet
(MAC/PHY on chip)
USB 1.1 (SIE on chip)
GPSI
SPI
UART/Modem
Bluetooth HCI
www.ubicom.com
Figure 1-1 IP2012 / IP2022 Block Diagram
© 2001-2003 Ubicom, Inc. All rights reserved.
1
1 page  
www.DataSheet4U.com
1.2.6 Other Supported Functions
On-chip dedicated hardware also includes a PLL, an 8-
channel 10-bit ADC, general-purpose timers, single-cycle
multiplier, analog comparator, LFSR units, external
memory interface (IP2022 only), parallel slave port,
brown-out power voltage detector, watchdog timer, low-
power support, multi-source wakeup capability, user-
selectable clock modes, high-current outputs, and 52
general-purpose I/O pins (48 on IP2012).
1.2.7 Programming and Debugging
Support
The IP2000 series has advanced in-system programming
and debug support on-chip. This unobtrusive capability is
provided through the ISP/ISD interface. There is no need
for a bond-out chip for software development. This
eliminates concerns about differences in electrical
characteristics between a bond-out chip and the actual
chip used in the target application. Designers can test and
revise code on the same part used in the actual
application.
Ubicom provides the complete Red Hat GNUPro tools,
including C compiler, assembler, linker, utilities and GNU
debugger. In addition, Ubicom offers an integrated
graphical development environment which includes an
editor, project manager, graphical user interface for the
GNU debugger, device programmer, and ipModule™
configuration tool.
IP2012 / IP2022 Data Sheet
www.ubicom.com
5
5 Page 
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IP2012 / IP2022 Data Sheet
Name
RE1
Pin
PQFP µBGA
42 H9
RE2 43 J10
RE3 44 J9
RE4 45 H10
RE5 46 G9
RE6 47 G10
RE7 48 J8
RF0 49 F7
RF1 50 F9
RF2 51 F10
RF3 52
RF4 57
RF5 58
RF6 59
RF7 60
RG0
61
RG1
62
RG2
63
RG3
64
RG4
66
RG5
67
RG6
68
RG7
69
* GVDD = 2.5V
F6
B9
A9
D10
D9
C10
C9
B10
A10
B7
B8
A7
D7
Table 2-1 Signal Descriptions (continued)
Type
Sink Source
@ 3.3V @ 3.3V
IOVDD IOVDD
Function
I/O 8 mA 8 mA I/O Port, S1RXP - VP (USB), SS (SPI Slave), TxEN
(GPSI Master), RxEN (GPSI Slave)
I/O 8 mA 8 mA I/O Port, S1RXM - VM (USB)
I/O 8 mA 8 mA I/O Port, S1RXD - RCV (USB), RXD (UART), DI
(SPI), TxD (GPSI Master), RxD (GPSI Slave)
I/O 8 mA 8 mA I/O Port, S1TXPE/S1OE - TxD+ (Ethernet), OE
(USB), RxEN (GPSI Master), TxEN (GPSI Slave)
I/O 24 mA 24 mA I/O Port, High Power Output, S1TXP - Tx+ (Ethernet),
VPO (USB), TXD (UART), DO (SPI), RxD (GPSI
Master), TxD (GPSI Slave)
I/O 24 mA 24 mA I/O Port, High Power Output, S1TXM - Tx- (Ethernet),
VMO (USB), TxCLK/RxCLK (GPSI Master), TxCLK
(GPSI Slave)
I/O 8 mA 8 mA I/O Port, S1TXME - TxD- (Ethernet), TxBUSY (GPSI)
I/O 8 mA 8 mA I/O Port, S2TXPE/S2OE - TxD+ (Ethernet), OE
(USB), RxEN (GPSI Master), TxEN (GPSI Slave)
I/O 24 mA 24 mA I/O Port, High Power Output, S2TXP - Tx+ (Ethernet),
VPO (USB), TXD (UART), DO (SPI), RxD (GPSI
Master), TxD (GPSI Slave)
I/O 24 mA 24 mA I/O Port, High Power Output, S2TXM - Tx- (Ethernet),
VMO (USB), TxCLK/RxCLK (GPSI Master), TxCLK
(GPSI Slave)
I/O 8 mA 8 mA I/O Port, S2TXME - TxD- (Ethernet), TxBUSY (GPSI)
I/O 8 mA 8 mA I/O Port, S2CLK - SCLK (SPI), RxCLK (GPSI),
optional SERDES clock input for UART or USB.
I/O 8 mA 8 mA I/O Port, S2RXP - VP (USB), SS (SPI Slave), TxEN
(GPSI Master), RxEN (GPSI Slave)
I/O 8 mA 8 mA I/O Port, S2RXM - VM (USB)
I/O 8 mA 8 mA I/O Port, S2RXD - RCV (USB), RXD (UART), DI
(SPI), TxD (GPSI Master), RxD (GPSI Slave)
AI/DO 4 mA* 4 mA* Output Port, ADC0 Input, Comparator Output
AI/DO 4 mA* 4 mA* Output Port, ADC1 Input, Comparator – Input
AI/DO 4 mA* 4 mA* Output Port, ADC2 Input, Comparator + Input
AI/DO 4 mA* 4 mA* Output Port, ADC3 Input, ADC reference Input
AI/DO 4 mA* 4 mA* Output Port, ADC4 Input, S1RX-
AI/DO 4 mA* 4 mA* Output Port, ADC5 Input, S1RX+
AI/DO 4 mA* 4 mA* Output Port, ADC6 Input, S2RX-
AI/DO 4 mA* 4 mA* Output Port, ADC7 Input, S2RX+
www.ubicom.com
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IP2022.PDF ] | |
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