DataSheet.es    


PDF 5236QSCX Data sheet ( Hoja de datos )

Número de pieza 5236QSCX
Descripción FAN5236QSCX
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de 5236QSCX (archivo pdf) en la parte inferior de esta página.


Total 20 Páginas

No Preview Available ! 5236QSCX Hoja de datos, Descripción, Manual

www.DataSheet4U.com
www.fairchildsemi.com
FAN5236
Dual Mobile-Friendly DDR / Dual-output PWM Controller
Features
• Highly flexible dual synchronous switching PWM
controller includes modes for:
– DDR mode with in-phase operation for reduced
channel interference
– 90˚ phase shifted two-stage DDR Mode for reduced
input ripple
– Dual Independent regulators 180° phase shifted
• Complete DDR Memory power solution
– VTT Tracks VDDQ/2
– VDDQ/2 Buffered Reference Output
• Lossless current sensing on low-side MOSFET or
precision over-current using sense resistor
• VCC Under-voltage Lockout
• Converters can operate from +5V or 3.3V or Battery
power input (5 to 24V)
• Excellent dynamic response with Voltage Feed-Forward
and Average Current Mode control
• Power-Good Signal
• Also supports DDR-II and HSTL
• Light load Hysteretic mode maximizes efficiency
• QSOP28, TSSOP28
Applications
• DDR VDDQ and VTT voltage generation
• Mobile PC dual regulator
• Server DDR power
• Hand-Held PC power
General Description
The FAN5236 PWM controller provides high efficiency and
regulation for two output voltages adjustable in the range
from 0.9V to 5.5V that are required to power I/O, chip-sets,
and memory banks in high-performance notebook comput-
ers, PDAs and Internet appliances. Synchronous rectification
and hysteretic operation at light loads contribute to a high
efficiency over a wide range of loads. The hysteretic mode of
operation can be disabled separately on each PWM converter
if PWM mode is desired for all load levels. Efficiency is even
further enhanced by using MOSFET’s RDS(ON) as a current
sense component.
Feed-forward ramp modulation, average current mode con-
trol scheme, and internal feedback compensation provide
fast response to load transients. Out-of-phase operation with
180 degree phase shift reduces input current ripple. The con-
troller can be transformed into a complete DDR memory
power supply solution by activating a designated pin. In
DDR mode of operation one of the channels tracks the out-
put voltage of another channel and provides output current
sink and source capability — features essential for proper
powering of DDR chips. The buffered reference voltage
required by this type of memory is also provided. The
FAN5236 monitors these outputs and generates separate
PGx (power good) signals when the soft-start is completed
and the output is within ±10% of its set point. A built-in
over-voltage protection prevents the output voltage from
going above 120% of the set point. Normal operation is auto-
matically restored when the over-voltage conditions go
away. Under-voltage protection latches the chip off when
either output drops below 75% of its set value after the soft-
start sequence for this output is completed. An adjustable
over-current function monitors the output current by sensing
the voltage drop across the lower MOSFET. If precision cur-
rent-sensing is required, an external current-sense resistor
may optionally be used.
REV. 1.1.7 4/4/03

1 page




5236QSCX pdf
www.DataSheet4U.com
FAN5236
PRODUCT SPECIFICATION
Electrical Specifications Recommended operating conditions, unless otherwise noted.
Parameter
Conditions
Power Supplies
VCC Current
LDRV, HDRV Open, VSEN forced
above regulation point
Shut-down (EN=0)
VIN Current – Sinking
VIN = 24V
VIN Current – Sourcing
VIN = 0V
VIN Current – Shut-down
UVLO Threshold
Rising VCC
Falling
UVLO Hysteresis
Oscillator
Frequency
Ramp Amplitude, pk–pk
VIN = 16V
Ramp Amplitude, pk–pk
VIN = 5V
Ramp Offset
Ramp / VIN Gain
VIN 3V
Ramp / VIN Gain
1V < VIN < 3V
Reference and Soft Start
Internal Reference Voltage
Soft Start current (ISS)
Soft Start Complete Threshold
at start-up
PWM Converters
Load Regulation
VSEN Bias Current
IOUTX from 0 to 5A, VIN from 5 to 24V
VOUT pin input impedance
Under-voltage Shutdown
as % of set point. 2µS noise filter
Over-voltage threshold
as % of set point. 2µS noise filter
ISNS Over-Current threshold
Output Drivers
RILIM= 68.5Ksee Figure 11.
HDRV Output Resistance
Sourcing
Sinking
LDRV Output Resistance
Sourcing
Sinking
PG (Power Good Output) and Control pins
Lower Threshold
as % of set point, 2µS noise filter
Upper Threshold
as % of set point, 2µS noise filter
PG Output Low
IPG = 4mA
Leakage Current
PG2/REF2OUT Voltage
VPULLUP = 5V
DDR = 1, 0 mA < IREF2OUT 10mA
Min.
10
4.3
4.1
255
0.891
-2
50
45
70
115
112
–86
108
99
Typ.
2.2
–15
4.55
4.25
300
300
2
1.25
0.5
125
250
0.9
5
1.5
80
55
75
120
140
12
2.4
12
1.2
Max. Units
3.0 mA
30 µA
30 µA
–30 µA
1 µA
4.75 V
4.45 V
mV
345 KHz
V
V
V
mV/V
mV/V
0.909
V
µA
V
+2 %
120 nA
65 K
80 %
125 %
168 µA
15
4
15
2
–94 %
116 %
0.5 V
1 µA
1.01 %
VREF2
REV. 1.1.7 4/4/03
5

5 Page





5236QSCX arduino
www.DataSheet4U.com
FAN5236
PRODUCT SPECIFICATION
Hysteretic Mode
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 consecutive
cycles.
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load increase
causes an instantaneous decrease in the output voltage due to
the voltage drop on the output capacitor ESR. If the load
causes the output voltage (as presented at VSNS) to drop
below the hysteretic regulation level (20mV below VREF),
the mode is changed to PWM on the next clock cycle.
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchronous
rectifier, where the voltage across ( VDS(ON) ) it is monitored,
and it is switched off when VDS(ON) goes positive (current
flowing back from the load) allowing the diode to block
reverse conduction.
The hysteretic comparator initiates a PFM signal to turn on
HDRV at the rising edge of the next oscillator clock, when
the output voltage (at VSNS) falls below the lower threshold
(10mV below VREF) and terminates the PFM signal when
VSNS rises over the higher threshold (5mV above VREF).
The switching frequency is primarily a function of:
1. Spread between the two hysteretic thresholds
2. ILOAD
3. Output Inductor and Capacitor ESR
A transition back to PWM (Continuous Conduction Mode or
CCM) mode occurs when the inductor current rises suffi-
ciently to stay positive for 8 consecutive cycles. This occurs
when:
ILOAD(CCM) = -----V----H---2-Y----SE---T-S--E-R--R---E----S---I--S-
(3)
where VHYSTERESIS = 15mV and ESR is the equivalent
series resistance of COUT.
Because of the different control mechanisms, the value of the
load current where transition into CCM operation takes place
is typically higher compared to the load level at which transi-
tion into hysteretic mode occurs. Hysteretic mode can be
disabled by setting the FPWM pin low.
VSEN
CSS SS
300K
0.17pf
1.5M 17pf
4.14K
TO PWM COMP
Reference and
Soft Start
ILIM det.
S/H
V to I
I1A =
ISNS
I1B =
ISNS
9
in +
in ñ
2.5V
0.9V
I2 = 4 * ILIM
3
ILIM mirror
ISNS RSENSE
LDRV
PGND
ILIM RILIM
Figure 11. Current Limit / Summing Circuits
REV. 1.1.7 4/4/03
11

11 Page







PáginasTotal 20 Páginas
PDF Descargar[ Datasheet 5236QSCX.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
5236QSCX FAN5236QSCXFairchild Semiconductor
Fairchild Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar