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PDF STEL-2060CR Data sheet ( Hoja de datos )
| Número de pieza | STEL-2060CR | |
| Descripción | 45Mbps Viterbi Decoder | |
| Fabricantes | Intel | |
| Logotipo |  |
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STEL-2060C/CR
Data Sheet
STEL-2060C/CR
45 Mbps
Viterbi Decoder
R
1 page  
www.DataSheet4U.com
DSCRAM
When this input is set high, it causes the G2 symbols to be
inverted before they enter the Viterbi decoder, thereby
reversing the effect of the G2 inversion if an "Invert G2"
scrambler is implemented at the encoder.
PNCG1, PNCG2
The PNCG1 and PNCG2 signals are used to control the
STEL-2060CCC when operating in punctured modes not
supported by the internal puncturing logic. In normal
operation (Rate 1/2 and when using internal puncturing)
these pins should be set low. In the external depuncturing
mode, the PNCG1 signal must be set high to indicate that the
G1 symbol is punctured and the PNCG2 signal must be set
high to indicate that the G2 symbol is punctured. A symbol
will be depunctured when the PNCG1 or PNCG2 signals are
high during the rising edge of SYMCKIN which latches the
corresponding symbol in to the decoder. RATE2-0 should be
set to 000 when operating in external depuncturing mode.
Zero value metrics will be substituted internally for the
actual metrics corresponding to the signals present on the
G12-0 and G22-0 pins at that time. Internal depuncturing can
be selected by the use of the RATE inputs.
SYNC
When the SYNC input is set high during the rising edge of
SYMCKIN the internal symbol synchronization will be
changed. When auto node sync is not desired this pin should
be set low. It should be connected to the AUTO output to use
the auto node sync capability of the STEL-2060CCC. The
state of this circuit will always be set to normal after a reset.
COUNT7-0
The 8-bit COUNT7-0 input defines the period (number of
bits) used in the node synchronization circuit when EXTSEL
is set high. The 8-bit number N is used to set up a period of
(256N + 256) bits internally, where N is the value of
COUNT7-0. An out-of-sync condition is declared (i.e., the
output pin OOS is set high and AUTO pulses high) if the
renormalization count exceeds the threshold value during a
period of this number of bits.
THR7-0
The 8-bit THR7-0 input defines the threshold for node
synchronization when EXTSEL is set high. The 8-bit number
N is used to set up a threshold value of (8N + 6) internally,
where N is the value of THR7-0. An out-of-sync condition is
declared (i.e., the output pin OOS is set high and AUTO
pulses high) if the renormalization count exceeds this
threshold value.
EXTSEL
When the EXTSEL input is set high, the COUNT7-0 and
THR7-0 information is derived from the COUNT7-0 and
THR7-0 input pins. When it is set low, this information is
derived from the data written into addresses 0 and 1.
OUTPUT SIGNALS
ODCLK
Output data clock. All outputs change on the rising edge of
this clock. The falling edge of ODCLK can be used as a strobe
for DATO output, which is guaranteed to be valid on this
edge.
DATO
Decoded data output. This is the output of the Viterbi
decoder. This signal changes on the rising edges of ODCLK.
In Rate 1/2 operation there will be a pipeline delay of 526
cycles of ODCLK from the G12-0/G22-0 inputs to the DATO
output when DDIF is set low and PARL is set high. Setting
DDIF high adds one cycle to this value and setting PARL low
adds two cycles.
OOS
This output pin serves as a flag for the out-of-sync condition.
When it goes high it signifies that the renormalization count
in the internal node sync circuit has exceeded the threshold
value set by the THR7-0 signal, declaring an out-of-sync
condition. It will remain high until this condition ceases to
exist. i.e., until the next time the threshold is not exceeded
during a complete count period.
AUTO
This is the feedback signal from the internal node sync
correction circuit. It will pulse high for one cycle of DCLKIN
each time the renormalization count in the internal node
sync circuit has exceeded the threshold value set by the
THR7-0 signal and the out-of-sync condition is declared. It
should be connected to the SYNC input when using the
internal node sync facility.
BERR
The Bit Error output indicates that an error has been detected
in either the G1 or G2 symbols corresponding to the current
output bit.
G1ERR
The G1 Error output indicates that an error has been detected
in the G1 symbol corresponding to the current output bit.
G2ERR
The G2 Error output indicates that an error has been detected
in the G2 symbol corresponding to the current output bit.
Note: The BERR, G1ERR and G2ERR signals are in NRZ
format, i.e., the signals will not return to zero between two
consecutive errors. To generate pulsed outputs, the signals
can be gated with the ODCLK signal.
MICROPROCESSOR INTERFACE
DATA7-0
All I/O and control functions can be accessed via the
DATA7-0 bus with the associated control signals. The
STEL-2060CCC is used as a memory or I/O mapped
peripheral to the host processor.
5 STEL-2060C
5 Page 
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A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 ±5% volts, Ta = 0° to 70° C)
Symbol
Parameter
Min.
fDAT
fDAT
Data speed, Parallel input mode (PARL = 1),
all rates when not using Internal Depuncturing
Data speed, Sequential input mode (PARL = 0), Rate 1/2
and all rates and modes when using Internal Depuncturing
tSU G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Setup
tHD G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Hold
tSUI G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Setup
tHDI G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Hold
tSHPE, tSLPE SYMCKIN Pulse width (high or low), Parallel input mode,
all rates when not using Internal Depuncturing
tSHPI, tSLPI SYMCKIN Pulse width (high or low), Parallel input mode,
all rates when using Internal Depuncturing
tSHS, tSLS SYMCKIN Pulse width (high or low), Serial input mode
tSO SYMCKIN to ODCLK stable delay (RATE2-0 = 000)
tDO DCLKIN to ODCLK stable delay (RATE2-0 ≠ 000)
tOD ODCLK to output stable delay, all other outputs
3
5
6
6
10
12
6
3
3
1
Max.
45
45
8
8
3
Units
Mbps
Mbps
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
nsecs.
Conditions
}PARL = 1 and
RATE2-0 = 0
}PARL = 0 or
RATE2-0 ≠ 0
}PARL = 0 or
RATE2-0 = 0
}PARL = 1 and
RATE2-0 ≠ 0
}PARL = 1 and
RATE2-0 = 0
}PARL = 1 and
RATE2-0 ≠ 0
PARL = 0
Load = 15 pF
Load = 15 pF
11 STEL-2060C
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet STEL-2060CR.PDF ] | |
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