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PDF K4X56323PG Data sheet ( Hoja de datos )

Número de pieza K4X56323PG
Descripción 8M x32 Mobile-DDR SDRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K4X56323PG Hoja de datos, Descripción, Manual

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K4X56323PG - 7(8)E/G
Mobile-DDR SDRAM
8M x32 Mobile-DDR SDRAM
FEATURES
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• Deep Power Down Mode
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
Auto refresh duty cycle
- 15.6us for -25 to 85 °C
Operating Frequency
Speed @CL2*1
Speed @CL3*1
Note :
1. CAS Latency
DDR266
83Mhz
133Mhz
Address configuration
Organization
8M x32
- DM is internally loaded to match DQ and DQS identically.
Bank
BA0,BA1
DDR222
66Mhz
111Mhz
Row
A0 - A11
Column
A0 - A8
Ordering Information
Part No.
K4X56323PG-7(8)E/GC3
K4X56323PG-7(8)E/GCA
Max Freq.
133MHz(CL=3),83MHz(CL=2)
111MHz(CL=3),66MHz(CL=2)
- 7(8)E 90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C)
- 7(8)G : 90 FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C)
- C3/CA : 133MHz(CL=3)/111MHz(CL=3)
Interface
LVCMOS
Package
90FBGA
Pb (Pb Free)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
January 2006

1 page




K4X56323PG pdf
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K4X56323PG - 7(8)E/G
Functional Description
Mobile-DDR SDRAM
POWER
APPLIED
POWER
ON
PRECHARGE
ALL BANKS
EMRS
MRS
CKEH
MRS
DEEP
POWER
DOWN
DEEP
POWER
DOWN
PARTIAL
SELF
REFRESH SELF
REFRESH
REFS
IDLE
ALL BANKS
PRECHARGED
REFSX
REFA
CKEL
AUTO
REFRESH
CKEH
ACT
POWER
DOWN
POWER
DOWN
CKEH
CKEL
WRITE
ROW
ACTIVE
BURST STOP
READ
WRITEA
WRITE
WRITEA READA
READ
READ
WRITEA
WRITEA
READA
PRE
PRE
PRE
READA
READA
PRE
PRECHARGE
PREALL
Figure.1 State diagram
Automatic Sequence
Command Sequence
January 2006

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K4X56323PG arduino
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K4X56323PG - 7(8)E/G
Mobile-DDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR266 DDR222 Unit
Operating Current
(One Bank Active)
IDD0 tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
65
65 mA
Precharge Standby Current in
power-down mode
all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are
IDD2P SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control
IDD2PS inputs are SWITCHING; data bus inputs are STABLE
0.3
0.3
mA
Precharge Standby Current
in non power-down mode
IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are
SWITCHING; data bus inputs are STABLE
IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
12
8
10
mA
6
Active Standby Current
in power-down mode
IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are
SWITCHING; data bus inputs are STABLE
IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control
inputs are SWITCHING; data bus inputs are STABLE
5
2
mA
Active Standby Current
in non power-down mode
(One Bank Active)
IDD3N one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs
are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
IDD3NS address and control inputs are SWITCHING; data bus inputs are STABLE
25
20
20
mA
15
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Deep Power Down Current
IDD4R one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are
SWITCHING; 50% data change each burst transfer
IDD5 tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs
are SWITCHING; data bus inputs are STABLE
CKE is LOW; tCK = tCKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
IDD6
TCSR Range
Full Array
-E 1/2 Array
1/4 Array
Full Array
-G 1/2 Array
1/4 Array
IDD8*2 Address and control inputs are STABLE; data bus inputs are STABLE
110 95
90 80
140 125
45*1
200
85
450
160 300
140 250
150 300
135 250
130 225
10
mA
mA
°C
uA
uA
Note :
1. It has +/- 5°C tolerance.
2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
3. IDD specifications are tested after the device is properly intialized.
4. Input slew rate is 1V/ns.
5. Definitions for IDD: LOW is defined as V IN 0.1 * V DDQ ;
HIGH is defined as V IN 0.9 * V DDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
January 2006

11 Page







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