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PDF X9312 Data sheet ( Hoja de datos )
| Número de pieza | X9312 | |
| Descripción | Terminal Voltage 0V to 15V | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9312 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Solid-state potentiometer
• 3-wire serial interface
• Terminal voltage, 0 to +15V
• 100 wiper tap points
—Wiper position stored in nonvolatile memory
and recalled on power-up
• 99 resistive elements
—Temperature compensated
—End to end resistance range ± 20%
• Low power CMOS
—VCC = 5V
—Active current, 3mA max.
—Standby current, 1mA max.
• High reliability
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
• RTOTAL values = 10kΩ, 50kΩ, and 100kΩ
• Packages
—8-lead SOIC and DIP
BLOCK DIAGRAM
X9312
Terminal Voltage 0V to +15V, 100 Taps
March 15, 2005
FN8176.0
DESCRIPTION
The Intersil X9312 is a digitally controlled
potentiometer (XDCP). The device consists of a
resistor array, wiper switches, a control section, and
nonvolatile memory. The wiper position is controlled
by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper
switching network. Between each element and at
either end are tap points accessible to the wiper
terminal. The position of the wiper element is
controlled by the CS, U/D, and INC inputs. The
position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent
power-up operation.
The device can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including:
– control
– parameter adjustments
– signal processing
VCC (Supply Voltage)
Up/Down
(U/D)
Increment
(INC)
Device Select
(CS)
Control
and
Memory
VSS (Ground)
General
U/D
INC
CS
RH/VH
RW/VW
RL/VL
VCC
VSS
7-Bit
Up/Down
Counter
7-Bit
Nonvolatile
Memory
Store and
Recall
Control
Circuitry
99
98
97
One 96
of
One
Hundred
Decoder
2
1
0
Transfer
Gates
Resistor
Array
Detailed
RH/VH
RL/VL
RW/VW
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
www.DataSheet4U.com
X9312
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Symbol
ICC
ISB
ILI
VIH
VIL
CIN(5)
Parameter
VCC active current (Increment)
Standby supply current
CS, INC, U/D input leakage current
CS, INC, U/D input HIGH voltage
CS, INC, U/D input LOW voltage
CS, INC, U/D input capacitance
Min.
Limits
Typ.(4)
1
Max.
3
500 1000
±10
2 VCC + 1
-1 0.8
10
Unit
mA
µA
µA
V
V
pF
Test Conditions
CS = VIL, U/D = VIL or VIH and
INC = 0.4V/2.4V @ max. tCYC
CS = VCC - 0.3V, U/D and
INC = VSS or VCC - 0.3V
VIN = VSS to VCC
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit
Years
Notes: (4) Typical values are for TA = 25°C and nominal supply voltage.
(5) This parameter is periodically sampled and not 100% tested.
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
VH/RH
VS Test Point
VW/RW
VL/RL
VH/RH
Test Point
VWW/RW
Force
VLL/RL
Current
RTOTAL
RH RL
CH
CW CL
10pF
10pF
25pF
RW
A.C. CONDITIONS OF TEST
Input pulse levels
Input rise and fall times
Input reference levels
0V to 3V
10ns
1.5V
5 FN8176.0
March 15, 2005
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet X9312.PDF ] | |
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