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PDF W83627DHG Data sheet ( Hoja de datos )

Número de pieza W83627DHG
Descripción LPC I/O
Fabricantes Winbond 
Logotipo Winbond Logotipo



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W83627DHG
WINBOND LPC I/O
Note: This document is for UBC, UBE and UBF version
except specified descriptions
Date : April 10, 2007 Version : 1.4

1 page




W83627DHG pdf
W83627DHG
PAGES DATES
11 N.A. 01/25/2007
12 N.A. 03/28/2007
13 N.A. 04/10/2007
VERSION
WEB
VERSION
4.
5.
1.
2.
3.
1.2 N.A. 4.
5.
6.
7.
8.
1.
1.3 N.A. 2.
3.
1.4 N.A. 1.
MAIN CONTENTS
Use “Tbase” instead of “TControl”
Add the pins, registers description and AC timing for
new ACPI function – VSBGATE#, ATXPGD,
FTPRST, PWROK2 and SUSC#
Modify the description for VSBGATE#, ATXPGD,
FTPRST.
Revise the definition for Logical Device A, CR[E5h]
bit 0.
Add new section of PWROK Generation in Chapter
14 Power Management Event.
Add new timing of VSBGATE# in Chapter 21
Specifications.
Modify the description of CR[2Ah], bits [7:4].
Modify the “t1” timing of RSMRST#.
Modify the descriptions of 7.7.2 OVT# Interrupt
Mode.
Modify the “t3” and “t4” timing in Table 14.4 and
section 21.3.3
Add a new DC spec. of RSMRST# PWROK for UBF
version (In section 14.3 and 14.4)
Add LPC Timing in section 21.4
Remove redundant Power on/off and LRESET#
Timing
Modify LPC Timing in section 21.4
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: Aug, 22, 2007
-III- Version 1.4

5 Page





W83627DHG arduino
W83627DHG
12.3.10 ECR (Extended Control Register) Mode = all ......................................................................155
12.3.11 ECP Pin Descriptions...........................................................................................................156
12.3.12 ECP Operation.....................................................................................................................157
12.3.13 FIFO Operation ....................................................................................................................158
12.3.14 DMA Transfers.....................................................................................................................158
12.3.15 Programmed I/O (NON-DMA) Mode ....................................................................................158
13. KEYBOARD CONTROLLER ........................................................................................................ 159
13.1 Output Buffer ....................................................................................................................... 159
13.2 Input Buffer.......................................................................................................................... 159
13.3 Status Register.................................................................................................................... 160
13.4 Commands .......................................................................................................................... 160
13.5 Hardware GATEA20/Keyboard Reset Control Logic .......................................................... 162
13.5.1 KB Control Register .............................................................................................................162
13.5.2 Port 92 Control Register.......................................................................................................163
14. POWER MANAGEMENT EVENT ................................................................................................ 164
14.1 Power Control Logic............................................................................................................ 164
14.1.1 PSON# Logic .......................................................................................................................165
14.1.2 AC Power Failure Resume...................................................................................................166
14.2 Wake Up the System by Keyboard and Mouse .................................................................. 167
14.2.1 Waken up by Keyboard events ............................................................................................167
14.2.2 Waken up by Mouse events.................................................................................................167
14.3 Resume Reset Logic........................................................................................................... 168
14.4 PWROK Generation............................................................................................................ 169
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF
Version Only.......................................................................................................................................170
15. SERIALIZED IRQ.......................................................................................................................... 173
15.1 Start Frame ......................................................................................................................... 173
15.2 IRQ/Data Frame.................................................................................................................. 174
15.3 Stop Frame.......................................................................................................................... 175
16. WATCHDOG TIMER .................................................................................................................... 176
17. GENERAL PURPOSE I/O ............................................................................................................ 177
18. VID INPUTS AND OUTPUTS ....................................................................................................... 178
18.1 VID Input Detection ............................................................................................................. 178
18.2 VID Output Control.............................................................................................................. 178
19. PCI RESET BUFFERS ................................................................................................................. 179
20. CONFIGURATION REGISTER .................................................................................................... 180
20.1 Chip (Global) Control Register ............................................................................................ 180
20.2 Logical Device 0 (FDC) ....................................................................................................... 187
20.3 Logical Device 1 (Parallel Port)........................................................................................... 190
20.4 Logical Device 2 (UART A) ................................................................................................. 191
20.5 Logical Device 3 (UART B) ................................................................................................. 191
20.6 Logical Device 5 (Keyboard Controller) .............................................................................. 193
Publication Release Date: Aug, 22, 2007
-IX- Version 1.4

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