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PDF G2996 Data sheet ( Hoja de datos )
| Número de pieza | G2996 | |
| Descripción | DDR I/II Termination Regulator | |
| Fabricantes | Global Mixed-mode Technology | |
| Logotipo |  |
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Global Mixed-mode Technology Inc.
DDR I/II Termination Regulator
G2996
Features
Operation Supply Voltage: 1.6V to 5.5V
Low Supply Current: 280µA @ 2.5V
Low Output Offset
Source and Sink Current
Low External Component Count
No Inductor Required
No external Resistors Required
Thermal Shutdown Protection
Suspend to RAM (STR) function
SOP-8 with Power-Pad package
Applications
DDR-SDRAM Termination Voltage
DDR-I / DDR-II Termination Voltage
SSTL-2
SSTL-3
General Description
The G2996 is a linear regulator designed to meet the
JEDEC SSTL-18 ,SSTL-2 and SSTL-3 (Series Stub
Termination Logic) specifications for termination of
DDR-SDRAM. It contains a high-speed operational
amplifier that provides excellent response to the load
transients. This device can deliver 1.5A/0.9A continu-
ous current and transient peaks up to 3A/1.8A in the
application as required for DDRI/II-SDRAM termination.
With an independent VSENSE pin, the G2996 can pro-
vide superior load regulation. The G2996 provides a
VREF output as the reference for the applications of the
chipset and DIMMs.
The G2996 can easily provide the accurate VTT and
VREF voltages without external resistors that PCB ar-
eas can be reduced. The quiescent current is as low
as 280µA @ 2.5V. So the power consumption can
meet the low power consumption applications.
The G2996 also has an active low shutdown ( SD ) pin
that provides Suspend to RAM (STR) functionality.
When SD is pulled low, the VTT output will be tri-state
providing a high impendence, but VREF will remain ac-
tive. A power saving advantage can be obtained in this
mode through lowering the quiescent current to180µA
@ 2.5V.
Ordering Information
ORDER
NUMBER
ORDER NUMBER
(Pb free)
G2996P1U
G2996P1Uf
G2996F1U
G2996F1Uf
Note: P1:SOP-8
F1:SOP-8(FD)
U: Tape & Reel (FD): Thermal Pad
Pin Configuration
MARKING
G2996
G2996
TEMP.
RANGE
-40°C to 85°C
-40°C to 85°C
PACKAGE
SOP-8
SOP-8 (FD)
Typical Application Circuit
GND 1
SD 2
VSENSE 3
VREF 4
G2996
SOP-8
8 VTT
7 PVIN
6 AVIN
5 VDDQ
Thermal
Pad
SD
VDDQ=2.5V
VDD=2.5V
47µF +
SD
VDDQ
VREF
AVIN
VSENSE
PVIN
VTT
GND
+
VREF=1.25V
0.01µF
VTT=1.25V
+ 220µF
Ver: 2.3
May 16, 2006
TEL: 886-3-5788833
http://www.gmt.com.tw
1
1 page  
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Global Mixed-mode Technology Inc.
G2996
Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C,
unless otherwise noted.
IQ vs AVIN in SD
160
150
140
130
120
110
100
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
IQ vs AVIN
270
250
230
210
190
170
150
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
VIH and VIL
2
1.8
1.6
VIH
1.4
VIL
1.2
1
0.8
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
VREF vs IREF
1.3
1.28
1.26
IO=200m
1.24
1.22
1.2
1.18
-30 -20 -10 0 10 20 30
IREF(µA)
VREF vs VDDQ
3
2.5
2
1.5
1
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5
VDDQ(V)
VTT vs IOUT Temperature
1.252
1.248
1.244
1.24
0°C
1.236
25°C
85°C
1.232
-100 -75 -50 -25 0 25 50 75 100
IOUT(mA)
Ver: 2.3
May 16, 2006
TEL: 886-3-5788833
http://www.gmt.com.tw
5
5 Page 
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Global Mixed-mode Technology Inc.
G2996
In Figure 5 & 6, they are the application configurations
of DDR-II SDRAM bus terminations. Figure 5 is the
typical application scheme of DDR-II SDRAM. With the
separate VDDQ pin and an internal resistor divider, it
is possible to use the G2996 in applications utilizing
DDR-II memory. Figure 6 is used to increase the driv-
ing capability. The risk is the same as figure 4.
SD
VDDQ=1.8V
AVIN=1.8V or 5.5V
PVIN=1.8V
CIN +
SD
VDDQ
AVIN
PVIN
VREF
VSENSE
VTT
GND
+ VREF=0.9V
CREF
VTT=0.9V
+
COUT
Figure 5. Recommended DDR-II Termination
SD
VDDQ=1.8V
AVIN=3.3V or 5.5V
PVIN=3.3V
CIN +
SD
VDDQ
AVIN
PVIN
VREF
VSENSE
VTT
GND
+ VREF=0.9V
CREF
VTT=0.9V
+
COUT
Figure 6. DDR-II Termination with higher voltage rails
Figure 7 & 8 are used to scale the VTT to the wanted
value when the standard voltages of SSTL-2 do not
meet the requirements. Using R1 & R2, figure 7 can
shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can
shift VTT down to VDDQ/2 * (1-R1/R2).
VDDQ
VDD
CIN +
VDDQ
AVIN
VTT
PVIN
VSENSE
GND
VTT
R1 +
COUT
R2
Figure 7. Increasing VTT by Level Shifting
VDDQ
VDD
CIN +
VDDQ
VSENSE
AVIN
PVIN
VTT
GND
R2
R1
VTT
+
COUT
Figure 8. Decreasing VTT by Level Shifting
Ver: 2.3
May 16, 2006
TEL: 886-3-5788833
http://www.gmt.com.tw
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet G2996.PDF ] | |
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