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PDF K9F1G08U0B Data sheet ( Hoja de datos )

Número de pieza K9F1G08U0B
Descripción Flash Memory
Fabricantes Samsung Electronics 
Logotipo Samsung Electronics Logotipo



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K9F1G08U0B
FLASH MEMORY
K9XXG08UXB
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K9F1G08U0B
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
CLE The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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K9F1G08U0B
FLASH MEMORY
AC Characteristics for Operation
Parameter
Symbol
Min
Data Transfer from Cell to Register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
CE Access Time
RE High to Output Hi-Z
CE High to Output Hi-Z
CE High to ALE or CLE Don’t Care
RE High to Output Hold
RE Low to Output Hold
tR
tAR
tCLR
tRR
tRP
tWB
tRC
tREA
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
-
10
10
20
12
-
25
-
-
-
-
10
15
5
CE High to Output Hold
RE High Hold Time
Output Hi-Z to RE Low
RE High to WE Low
WE High to RE Low
Device Resetting Time(Read/Program/Erase)
tCOH
tREH
tIR
tRHW
tWHR
tRST
15
10
0
100
60
-
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.
Max
25
-
-
-
-
100
-
20
25
100
30
-
-
-
-
-
-
-
-
5/10/500(1)
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
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