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PDF P1817B Data sheet ( Hoja de datos )
| Número de pieza | P1817B | |
| Descripción | Low-Power Mobile VGA EMI Reduction IC | |
| Fabricantes | Alliance Semiconductor | |
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www.DataSheet4U.com
October 2003
P1817A/B
rev 1.0
Low-Power Mobile VGA EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Generates a low EMI spread spectrum clock of the
input frequency.
Optimized for frequency range from:
o P1817A – 20 to 30MHz. Operation
o P1817B – 10 to 20MHz Operation
Internal loop filter minimizes external components
and board space.
Two selectable spread ranges.
Low inherent cycle-to-cycle jitter.
3.3V or 5V operating voltage range.
TTL or CMOS compatible outputs.
Ultra-low power CMOS design.
3.17mA @3.3V, 10MHz | [email protected], 10MHz
4.28mA @3.3V, 14MHz | 7.50mA @5.0V, 14MHz
5.50mA @3.3V, 20MHz | 9.50mA @5.0V, 20MHz
Supports notebook VGA and other LCD timing
controller applications.
SSON pin for Spread Spectrum On/Off and
Standby Mode controls.
Available in 8-pin SOIC and TSSOP.
Product Description
The P1817 is a versatile spread spectrum frequency
modulator designed specifically for input clock frequencies.
The P1817 reduces electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of
down stream clock and data dependent signals. The P1817
allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding and
other passive components that are traditionally required to
pass EMI regulations.
The P1817 modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
The P1817 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
Applications
The P1817 is targeted towards notebook VGA chip and
other displays using an LVDS interface, PC peripheral
devices, and embedded systems.
Block Diagram
SR0 SSON
VDD
XIN
XOUT
Crystal
Oscillator
Ref
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
www.DataSheet4U.com
October 2003
P1817A/B
rev 1.0
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
-0.5 to + 7.0
V
TSTG
Storage temperature
-65 to +125
°C
TA Operating temperature
0 to 70
°C
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol
VIL
VIH
IIL
IIH
IXOL
IXOH
VOL
VOH
ICC
IDD
VDD
tON
ZOUT
Parameter
Input low voltage
Input high voltage
Input low current (pull-up resistors on inputs SR0 and
SSON/SBM)
Input high current (pull-down resistor on input SSON#)
XOUT output low current
XOUT output high current
Output low voltage
Output high voltage
Dynamic supply current
normal mode
@ 0.4V, VDD = 3.3V
@ 0.4V, VDD = 5.0V
@ 2.5V, VDD = 3.3V
@ 4.5V, VDD = 5.0V
VDD =3.3V, IOL = 20mA
VDD =5.0V, IOL = 20mA
VDD =3.3V, IOH = 20mA
VDD =5.0V, IOH = 20mA
Normal Mode
3.3V and 10pF loading
5.0V and 10pF loading
Static supply current standby mode
Operating voltage
Power up time (first locked clock cycle after power up)
Clock output impedance
Min
GND – 0.3
2.0
-
-
-
-
-
-
-
-
2.5
4.5
fIN-min
3.2
6.2
-
2.7
-
-
Typ
-
-
-
-
3
20
3
20
-
-
-
-
fIN-typ
-
-
0.6
3.3
0.18
50
Max
0.8
VDD + 0.3
-35
35
-
-
-
-
0.4
-
-
-
fIN-max
7.0
13.6
-
5.5
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
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