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PDF VT6212 Data sheet ( Hoja de datos )
| Número de pieza | VT6212 | |
| Descripción | PCI USB2.0 Controller | |
| Fabricantes | Via | |
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Data Sheet
VT6212 /
VT6212L
PCI USB 2.0
Controller
Revision 1.06
December 7, 2005
VIA TECHNOLOGIES, INC.
1 page  
www.DataSheet4U.com
VT6212 / VT6212L PCI USB2.0 Controller
LIST OF FIGURES
FIGURE 1. VT6212 / VT6212L CHIP BLOCK DIAGRAM........................................................................................................ 2
FIGURE 2. VT6212 (PQFP) / VT6212L (LQFP) PIN DIAGRAM (TOP VIEW) ...................................................................... 3
FIGURE 3. MECHANICAL SPECIFICATIONS – 128 PIN PQFP (VT6212) / LQFP (VT6212L) PACKAGE .................. 19
FIGURE 4. LEAD-FREE MECHANICAL SPECIFICATIONS – 128 PIN PQFP (VT6212) / LQFP (VT6212L)
PACKAGE .................................................................................................................................................................. 20
Revision 1.06, December 7, 2005
-iii-
List of Figures
5 Page 
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Pin Descriptions
VT6212 / VT6212L PCI USB2.0 Controller
Table 2. VT6212 / VT6212L Pin Descriptions
PCI Interface
Signal Name
AD[31:0]
CBE[3 :0]#
PAR
IDSEL
DEVSEL#
FRAME#
STOP#
IRDY#
TRDY#
PCIRST#
PCICLK
INTA#
INTB#
INTC#
REQ#
GNT#
Pin # I/O Power Signal Description
(see pin IO VCC33 Address and Data. Addresses are passed during the first clock cycle. Data is
list) passed in subsequent cycles.
3, 19, IO VCC33 Command / Byte Enables. The command for the current cycle is driven with
28, 41
FRAME# assertion. Byte enables corresponding to supplied or requested data are
then driven on following clocks.
27 IO VCC33 Parity. A single parity bit is provided over AD[31:0] and CBE[3:0]# to check that
the data has been transferred accurately..
6 I VCC33 Initialization Device Select. Used as a chip select during configuration read and
write cycles.
23 IO VCC33 Device Select. As an output, this signal is asserted to claim PCI transactions
through positive or subtractive decoding. As an input, DEVSEL# indicates the
response to a VT6212-initiated transaction and is also sampled when decoding
whether to subtractively decode the cycle.
20 IO VCC33 Cycle Frame. Assertion indicates the address phase of a PCI transfer. Negation
indicates that one more data transfer is desired by the cycle initiator.
24 IO VCC33 PCI Stop. Asserted by the target (the VT6212 / VT6212L chip) to request the
master (PCI device) to stop the current transaction.
21 IO VCC33 Initiator Ready. Asserted when the initiator is ready for data transfer.
22 IO VCC33 Target Ready. Asserted when the target is ready for data transfer.
111 I VCC33 PCI Reset. When detected low, an internal hardware reset is performed. PCIRST#
assertion or deassertion may be asynchronous to PCICLK, however, it is
recommended that deassertion be synchronous to guarantee a clean and bounce free
edge.
109 I VCC33 PCI Clock. 33 MHz. Used to clock all PCI bus transactions.
105 O VCC33 PCI Interrupt A. Asynchronous signal used to request an interrupt.
106 O VCC33 PCI Interrupt B. Asynchronous signal used to request an interrupt.
107 O VCC33 PCI Interrupt C. Asynchronous signal used to request an interrupt.
113 O VCC33 PCI Bus Request. Asserted by the VT6212 / VT6212L to request bus use.
112 I VCC33 PCI Bus Grant. Asserted by the bus arbiter to grant permission to the VT6212 /
VT6212L for access to the PCI bus for bus master operations.
Signal Name
EECS
EECK
EEDI
EEDO
Pin #
56
55
50
49
Serial EEPROM Interface
I/O Power Signal Description
O VCC33 EEPROM Chip Select. Connect to EEPROM EECS pin.
O VCC33 EEPROM Clock. Connect to EEPROM EECK pin.
O VCC33 EEPROM Data In. Connect to EEPROM EEDI pin.
I VCC33 EEPROM Data Output. Connect to EEPROM EEDO pin.
Signal Name
SMI#
PME#
Chipset South Bridge Interface
Pin # I/O Power Signal Description
60 O VCC33 System Management Interrupt.
67 O VCCSUS Power Management Event Interrupt.
Revision 1.06, December 7, 2005
-5-
Pin Descriptions
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet VT6212.PDF ] | |
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