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PDF TA80C186XL Data sheet ( Hoja de datos )

Número de pieza TA80C186XL
Descripción (TA80C186XL / TA80C188XL) 16-Bit High Integration Embedded Processors
Fabricantes Intel 
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80C186XL 80C188XL
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y Low Power Fully Static Versions of
80C186 80C188
Y Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
(80C186XL Only)
Compatible Mode
NMOS 80186 80188 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y Speed Versions Available
25 MHz (80C186XL25 80C188XL25)
20 MHz (80C186XL20 80C188XL20)
12 MHz (80C186XL12 80C188XL12)
Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y Available in 68-Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier
(JEDEC A Package)
Y Available in 80-Pin
Quad Flat Pack (EIAJ)
Shrink Quad Flat Pack (SGFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor It offers higher speed
and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com-
patibility Packaging and pinout are also identical
272431-1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272431-004
COPYRIGHT INTEL CORPORATION 1995
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TA80C186XL pdf
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80C186XL 80C188XL
Bus Interface Unit
The 80C186XL provides a local bus controller to
generate the local bus control signals In addition it
employs a HOLD HLDA protocol for relinquishing
the local bus to other bus masters It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data
from the local bus during a read operation Synchro-
nous and asynchronous ready input pins are provid-
ed to extend a bus cycle beyond the minimum four
states (clocks)
The 80C186XL bus controller also generates two
control signals (DEN and DT R) when interfacing to
external transceiver chips This capability allows the
addition of transceivers for simple buffering of the
multiplexed address data bus
During RESET the local bus controller will perform
the following action
 Drive DEN RD and WR HIGH for one clock cy-
cle then float them
 Drive S0–S2 to the inactive state (all HIGH) and
then float
 Drive LOCK HIGH and then float
 Float AD0–15 (AD0–8) A16–19 (A9–A19) BHE
(RFSH) DT R
 Drive ALE LOW
 Drive HLDA LOW
RD QSMD UCS LCS MCS0 PEREQ MCS1
ERROR and TEST BUSY pins have internal pullup
devices which are active while RES is applied Ex-
cessive loading or grounding certain of these pins
causes the 80C186XL to enter an alternative mode
of operation
 RD QSMD low results in Queue Status Mode
 UCS and LCS low results in ONCE Mode
 TEST BUSY low (and high later) results in En-
hanced Mode
80C186XL PERIPHERAL
ARCHITECTURE
All the 80C186XL integrated peripherals are con-
trolled by 16-bit registers contained within an inter-
nal 256-byte control block The control block may be
mapped into either memory or I O space Internal
logic will recognize control block addresses and re-
spond to bus cycles An offset map of the 256-byte
control register block is shown in Figure 3
Chip-Select Ready Generation Logic
The 80C186XL contains logic which provides
programmable chip-select generation for both mem-
ories and peripherals In addition it can be
programmed to provide READY (or WAIT state) gen-
eration It can also provide latched address bits A1
and A2 The chip-select lines are active for all mem-
ory and I O cycles in their programmed areas
whether they be generated by the CPU or by the
integrated DMA unit
The 80C186XL provides 6 memory chip select out-
puts for 3 address areas upper memory lower
memory and midrange memory One each is provid-
ed for upper memory and lower memory while four
are provided for midrange memory
Relocation Register
OFFSET
FEH
DMA Descriptors Channel 1
DAH
D0H
DMA Descriptors Channel 0
CAH
C0H
Chip-Select Control Registers
A8H
A0H
Time 2 Control Registers
Time 1 Control Registers
Time 0 Control Registers
66H
60H
5EH
58H
56H
50H
Interrupt Controller Registers
3EH
20H
Figure 3 Internal Register Map
The 80C186XL provides a chip select called UCS
for the top of memory The top of memory is usually
used as the system memory because after reset the
80C186XL begins executing at memory location
FFFF0H
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TA80C186XL arduino
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80C186XL 80C188XL
Pin
Name
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
NMI
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
A19 S6
A18 S5
A17 S4
A16 S3
(A8 – A15)
AD0 – AD15
(AD0 – AD7)
Pin
Type
I
O
I
I
I
IO
O
IO
Table 3 Pin Descriptions (Continued)
Input Output
Type States
Pin Description
A(L)
A(E)
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs
H(Q)
R(1)
Timer outputs are used to provide single pulse or
continuous waveform generation depending upon the
timer mode selected These outputs are not floated
during a bus hold
A(L) DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
transfer These signals are level-triggered and internally
synchronized
A(E)
The Non-Maskable Interrupt input causes a Type 2
interrupt An NMI transition from LOW to HIGH is
latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be
asserted for at least one CLKOUT period The Non-
Maskable Interrupt cannot be avoided by programming
A(E)
A(L)
A(E)
A(L)
H(1)
R(Z)
Maskable Interrupt Requests can be requested by
activating one of these pins When configured as inputs
these pins are active HIGH Interrupt Requests are
synchronized internally INT2 and INT3 may be
configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To
ensure recognition all interrupt requests must remain
active until the interrupt is acknowledged When Slave
Mode is selected the function of these pins changes
(see Interrupt Controller section of this data sheet)
H(Z)
R(Z)
Address Bus Outputs and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T1
These signals are active HIGH
During T2 T3 TW and T4 the S6 pin is LOW to indicate
a CPU-initiated bus cycle or HIGH to indicate a DMA-
initiated or refresh bus cycle During the same T-states
S3 S4 and S5 are always LOW On the 80C188XL
A15 – A8 provide valid address information for the entire
bus cycle
S(L) H(Z) Address Data Bus signals constitute the time
R(Z)
multiplexed memory or I O address (T1) and data (T2
T3 TW and T4) bus The bus is active HIGH For the
80C186XL A0 is analogous to BHE for the lower byte of
the data bus pins D7 through D0 It is LOW during T1
when a byte is to be transferred onto the lower portion
of the bus in memory or I O operations
NOTE
Pin names in parentheses apply to the 80C188XL
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