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Número de pieza PCF5213
Descripción Microcontroller
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Freescale Semiconductor
Data Sheet
MCF5213EC
Rev. 0, 05/2005
MCF5213 Microcontroller Family
Hardware Specification
The MCF5213 is a member of the ColdFire® family of
reduced instruction set computing (RISC)
microprocessors. This hardware specification provides
an overview of the 32-bit MCF5213 microcontroller,
focusing on its highly integrated and diverse feature set.
Freescale reserves the right to change or discontinue this
product without notice. Specifications and information
herein are subject to change without notice.
This 32-bit device is based on the Version 2 ColdFire
core operating at a frequency up to 80 MHz, offering
high performance and low power consumption. On-chip
memories connected tightly to the processor core include
256 Kbytes of Flash and 32 Kbytes of static random
access memory (SRAM). On-chip modules include the
following:
• V2 ColdFire core delivering 76 MIPS
(Dhrystone 2.1) at 80 MHz running from
internal Flash with Multiply Accumulate (MAC)
Unit and hardware divider
• FlexCAN controller area network (CAN)
module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
Table of Contents
1 MCF5213 Family Configurations .........................2
1.1 Block Diagram ...................................................3
1.2 Features.............................................................4
1.3 Part Numbers and Packaging..........................14
1.4 Package Pinouts..............................................15
1.5 Reset Signals ..................................................20
1.6 PLL and Clock Signals ....................................20
1.7 Mode Selection................................................21
1.8 External Interrupt Signals ................................21
1.9 Queued Serial Peripheral Interface (QSPI) .....22
1.10 I2C I/O Signals.................................................22
1.11 UART Module Signals .....................................22
1.12 DMA Timer Signals..........................................23
1.15 Pulse Width Modulator Signals........................24
1.16 Debug Support Signals....................................24
1.17 EzPort Signal Descriptions ..............................26
1.18 Power and Ground Pins...................................26
2 Preliminary Electrical Characteristics................26
3 Mechanical Outline Drawings ............................42
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.

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MCF5213 Family Configurations
1.2.1 Feature Overview
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register, and
four new instructions for improved bit processing
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16 × 16 32 or
32 × 32 32 operations
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can
be configured into a 1- or 2-level trigger
• On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with
standby power supply support
— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• FlexCAN 2.0B Module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0-8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length
each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
Freescale Semiconductor
MCF5213 Microcontroller Family Hardware Specification, Rev. 0
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MCF5213 Family Configurations
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.2.5.2 Flash
The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to
generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The Flash memory is ideal for program and data
storage for single-chip applications, allowing for field reprogramming without requiring an external high
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the
Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath
for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming
interface that allows the Flash to be read, erased and programmed by an external controller in a format
compatible with most SPI bus Flash memory chips.
1.2.6 Power Management
The MCF5213 incorporates several low power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip
falls below the standby battery voltage.
1.2.7 FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific
requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of
FlexCAN has 16 message buffers.
1.2.8 UARTs
The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked
by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third
UART is multiplexed with other digital I/O functions.
1.2.9 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.
Freescale Semiconductor
MCF5213 Microcontroller Family Hardware Specification, Rev. 0
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