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PDF ICS9LPR501 Data sheet ( Hoja de datos )
| Número de pieza | ICS9LPR501 | |
| Descripción | 64-pin CK505 w/Fully Integrated Voltage Regulator | |
| Fabricantes | ICS | |
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Integrated
Circuit
Systems, Inc.
ICS9LPR501
64-pin CK505 w/Fully Integrated Voltage Regulator
Recommended Application:
CK505 compliant clock with fully integrated voltage regulator
Output Features:
• 2 - CPU differential low power push-pull pairs
• 10 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull
pair
• 1 - SRC/DOT selectable differential low power push-pull
pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Selectable between one SRC differential push-pull pair
and two single-ended outputs
Pin Configuration
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96_IO 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3_IO 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRC_IO 26
SRCT4 27
SRCC4 28
GNDSRC 29
SRCT9 30
SRCC9 31
SRCC11/CR#_G 32
64 SCLK
63 SDATA
62 REF0/FSLC/TEST_SEL
61 VDDREF
60 X1
59 X2
58 GNDREF
57 FSLB/TEST_MODE
56 CK_PWRGD/PD#
55 VDDCPU
54 CPUT0
53 CPUC0
52 GNDCPU
51 CPUT1_F
50 CPUC1_F
49 VDDCPU_IO
48 NC
47 CPUT2_ITP/SRCT8
46 CPUC2_ITP/SRCC8
45 VDDSRC_IO
44 SRCT7/CR#_F
43 SRCC7/CR#_E
42 GNDSRC
41 SRCT6
40 SRCC6
39 VDDSRC
38 PCI_STOP#/SRCT5
37 CPU_STOP#/SRCC5
36 VDDSRC_IO
35 SRCC10
34 SRCT10
33 SRCT11/CR#_H
64-pin TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Table 1: CPU Frequency Select Table
FSLC2
B0b7
FSLB1
B0b6
FSLA1
B0b5
CPU
MHz
SRC
MHz
PCI REF
MHz MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
11 1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
USB
MHz
48.00
DOT
MHz
96.00
1118E—08/08/07
1 page  
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Integrated
Circuit
Systems, Inc.
ICS9LPR501
Pin Description (Continued)
PIN #
PIN NAME
49 VDDCPU_IO
50 CPUC1_F
51 CPUT1_F
52 GNDCPU
53 CPUC0
54 CPUT0
55 VDDCPU
56 CK_PWRGD/PD#
57 FSLB/TEST_MODE
58 GNDREF
59 X2
60 X1
61 VDDREF
62 REF0/FSLC/TEST_SEL
63 SDATA
64 SCLK
TYPE
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
DESCRIPTION
Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance
Complement clock of low power differenatial CPU clock pair. This clock will be free-running
during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Fully Integrated Regulator Connection for Desktop/Mobile Applications
ICS9LPR501
VDDCPU_IO, Pin 49
NC
PIN 48
1.05V to 3.3V
(+/-5%)
CPU_IO Decoupling
Network
96_IO Decoupling
Network
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 45,36,26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
1118E—08/08/07
5
5 Page 
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9LPR501
Table 1: CPU Frequency Select Table
FSLC2
B0b7
FSLB1
B0b6
FSLA1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318 48.00
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
11 1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
Table 2: PLL3 Quick Configuration
B1b4
B1b3
B1b2
B1b1
Pin 17
MHz
00 0
0
00 0
1 100.00
00 1
0 100.00
00 1
1 100.00
01 0
0 100.00
01 0
1 100.00
01 1
0 100.00
01 1
1 N/A
10 0
0 24.576
10 0
1 24.576
10 1
0 98.304
10 1
1 27.000
11 0
0 25.000
11 0
1 27.000
11 1
0 N/A
11 1
1 N/A
Pin 18
MHz
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
98.304
98.304
27.000
25.000
27 SS
N/A
N/A
Spread
%
Comment
PLL 3 disabled
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0.5% Down Spread
Only SRCCLK1 from PLL3
1% Down Spread
Only SRCCLK1 from PLL3
1.5% Down Spread
Only SRCCLK1 from PLL3
2% Down Spread
Only SRCCLK1 from PLL3
2.5% Down Spread
Only SRCCLK1 from PLL3
N/A N/A
None
24.576Mhz on SE1 and SE2
None
24.576Mhz on SE1, 98.304Mhz on SE2
None
98.304Mhz on SE1 and SE2
None
27Mhz on SE1 and SE2
None
25Mhz on SE1 and SE2
-0.5% Down on Pin 18
27Mhz on SE1 and SE2
N/A N/A
N/A N/A
1118E—08/08/07
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ICS9LPR501.PDF ] | |
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