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Número de pieza | FDMS9620S | |
Descripción | 30V Dual N-Channel PowerTrench MOSFET | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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July 2007
FDMS9620S
Dual N-Channel PowerTrench® MOSFET
Q1: 30V, 16A, 21.5mΩ Q2: 30V, 18A, 13mΩ
tm
Features
Q1: N-Channel
Max rDS(on) = 21.5mΩ at VGS = 10V, ID = 7.5A
Max rDS(on) = 29.5mΩ at VGS = 4.5V, ID = 6.5A
Q2: N-Channel
Max rDS(on) = 13mΩ at VGS = 10V, ID = 10A
Max rDS(on) = 17mΩ at VGS = 4.5V, ID = 8.5A
Low Qg high side MOSFET
Low rDS(on) low side MOSFET
Thermally efficient dual Power 56 package
Pinout optimized for simple PCB design
RoHS Compliant
General Description
This device includes two specialized MOSFETs in a unique dual
Power 56 package. It is designed to provide an optimal
Synchronous Buck power stage in terms of efficiency and PCB
utilization. The low switching loss "High Side" MOSFET is
complemented by a Low Conduction Loss "Low Side" SyncFET.
Applications
Synchronous Buck Converter for:
Notebook System Power
General Purpose Point of Load
G1
D1
D1
D1 D1
G2
S2
S2
S1/D2
S2
Power 56
S2 5
S2 6
S2 7
G2 8
4 D1
3 D1
2 D1
1 G1
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous (Package limited) TC = 25°C
-Continuous (Silicon limited) TC = 25°C
-Continuous
TA = 25°C
-Pulsed
Power Dissipation for Single Operation
TA = 25°C
TA = 25°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Q1 Q2
30 30
±20 ±20
16 18
21 44
7.5 10
60 60
2.5
1
-55 to +150
Units
V
V
A
W
°C
RθJC
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
8.2 3.1
50
120
°C/W
Device Marking
FDMS9620S
Device
FDMS9620S
Package
Power 56
Reel Size
13”
Tape Width
12mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
1
www.fairchildsemi.com
1 page Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
10
ID = 7.5A
8
6
4
VDD =10V
VDD = 15V
VDD = 20V
2
0
0 2 4 6 8 10 12
Qg, GATE CHARGE(nC)
Figure 7. Gate Charge Characteristics
1000
Ciss
Coss
100
f = 1MHz
VGS = 0V
Crss
30
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
100 100 VGS = 10V
10
1 SINGLE PULSE
TJ = MAX RATE
RθJA = 120oC
0.1 TA = 25oC
THIS AREA IS LIMITED
BY rDS(ON)
0.01
0.1
1
1ms
10ms
100ms
1s
10s
DC
10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
10
1
0.5
10-3
SINGLE PULSE
RθJA = 120oC/W
TA= 25oC
10-2
10-1
100
101
t, PULSE WIDTH (s)
102
Figure 10. Single Pulse Maximum
Power Dissipation
103
2
1
0.1
0.01
10-3
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA = 120oC/W
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 11. Transient Thermal Response Curve
102
103
©2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
5
www.fairchildsemi.com
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet FDMS9620S.PDF ] |
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