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PDF P89CV51RB2 Data sheet ( Hoja de datos )
| Número de pieza | P89CV51RB2 | |
| Descripción | (P89CV51Rx2) 8-Bit Low Power 64Kb Flash Microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89CV51RB2/RC2/RD2
8-bit 80C51 5 V low power 64 kB flash microcontroller with
1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals
Rev. 01 — 21 May 2007
Product data sheet
1. General description
The P89CV51RB2/RC2/RD2 are 80C51 microcontrollers with 16 kB/32 kB/64 kB flash
and 1 kB of data RAM. These devices are designed to be drop-in and software compatible
replacements for the popular P89C51RB2/RC2/RD2 devices. Both the In-System
Programming (ISP) and In-Application Programming (IAP) boot codes are upward
compatible.
Additional features of the P89CV51RB2/RC2/RD2 device when compared to the
P89C51RB2/RC2/RD2 devices are the inclusion of an SPI interface, and increase in
RAM, and the ability to erase code memory in 128-byte pages.
The IAP capability combined with the 128-byte page size allows for efficient use of the
code memory for non-volatile data storage.
2. Features
2.1 Principal features
Supports 12-clock (default) or 6-clock mode selection via ISP or parallel programmer
6-clock/12-clock mode programmable “on-the-fly” by SFR bit
Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the
CPU is in 6-clock mode
128-byte page erase for efficient use of code memory as non-volatile data storage
0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode
16/32/64 kB of on-chip flash user code memory with ISP and IAP
1 kB RAM
SPI (Serial Peripheral Interface) and enhanced UART
PCA (Programmable Counter Array) with PWM and Capture/Compare functions
Three 16-bit timers/counters
2.2 Additional features
Four 8-bit I/O ports
WatchDog Timer (WDT)
30 ms page erase, 150 ms block erase
PLCC44 and TQFP44 packages
Ten interrupt sources with four priority levels
Second DPTR register
Low EMI mode (ALE inhibit)
1 page  
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NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
P1[5]/CEX2/MOSI 1
P1[6]/CEX3/MISO 2
P1[7]/CEX4/SPICLK 3
RST 4
P3[0]/RXD 5
n.c. 6
P3[1]/TXD 7
P3[2]/INT0 8
P3[3]/INT1 9
P3[4]/T0 10
P3[5]/T1 11
P89CV51RB2/RC2/RD2
33 P0[4]/AD4
32 P0[5]/AD5
31 P0[6]/AD6
30 P0[7]/AD7
29 EA
28 n.c.
27 ALE
26 PSEN
25 P2[7]/A15
24 P2[6]/A14
23 P2[5]/A13
002aac961
Fig 3. TQFP44 pin configuration
P89CV51RB2_RC2_RD2_1
Product data sheet
Rev. 01 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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Table 4. Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
MSB
Bit functions and addresses
LSB
DPL Data Pointer LOW
82H
Bit address AF AE AD AC AB AA A9 A8
IE* Interrupt Enable
A8H EA
EC ET2 ES ET1 EX1 ET0 EX0
Bit address BF BE BD BC BB BA B9 B8
IP* Interrupt Priority
B8H -
PPC
PT2
PS
PT1 PX1 PT0 PX0
IPH Interrupt Priority HIGH
B7H -
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit address
87
86
85
84
83
82
81
80
P0* Port 0
80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Bit address
97
96
95
94
93
92
91
90
P1* Port 1
90H CEX4/
CEX3/
CEX2/ CEX1/ SS CEX0
ECI
T2EX
SPICLK
MISO
MOSI
T2
Bit address A7 A6 A5 A4 A3 A2 A1 A0
P2* Port 2
A0H A15 A14 A13 A12 A11 A10
A9
A8
Bit address B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3
B0H RD WR T1
T0
INT1
INT0
TXD
RXD
PCON
Power Control Register
87H SMOD1 SMOD0
-
POF GF1 GF0
PD
IDL
Bit address D7 D6 D5 D4 D3 D2 D1 D0
PSW*
Program Status Word
D0H
CY
AC
F0 RS1 RS0 OV
F1
P
RCAP2H Timer2 Capture HIGH
CBH
RCAP2L Timer2 Capture LOW
CAH
Bit address
9F
9E
9D
9C
9B 9A
99
98
SCON*
Serial Port Control
98H SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SBUF
Serial Port Data Buffer Register
99H
SADDR
Serial Port Address Register
A9H
SADEN
Serial Port Address Enable
B9H
Bit address 87[1]
86[1]
85[1]
84[1]
83[1]
82[1]
81[1]
80[1]
SPCR
SPI Control Register
D5H
SPIE
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPSR
SPI Configuration Register
AAH
SPIF
WCOL
-
-
-
-
-
-
SPDAT
SPI Data
86H
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