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PDF GM2120 Data sheet ( Hoja de datos )

Número de pieza GM2120
Descripción (GM2110 / GM2120) XGA/SXGA LCD Monitor Controller
Fabricantes Genesis 
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Genesis Microchip Publication
PRELIMINARY DATA SHEET
gm2110 / gm2120
XGA/SXGA LCD Monitor Controller with
Integrated Analog Interface
*** Genesis Microchip Confidential ***
Publication number: C2120-DAT-01C
Publication date: June 2002
Genesis Microchip Inc.
2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: (91)-80-526-3878, Fax: (91)-80-529-6245
4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: 886-2-2791-0118 Fax: 886-2-2791-0196
143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942
Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874
2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759
www.genesis-microchip.com / [email protected]

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GM2120 pdf
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*** Genesis Microchip Confidential ***
gm2110/20 Preliminary Data Sheet
4.9 Gamma LUT .............................................................................................................................. 25
4.10 Display Output Interface.......................................................................................................... 25
4.10.1 Display Synchronization ............................................................................................ 25
4.10.2 Programming the Display Timing .............................................................................. 25
4.10.3 Panel Power Sequencing (PPWR, PBIAS) ................................................................ 27
4.10.4 Output Dithering......................................................................................................... 27
4.11 Energy Spectrum Management (ESM) .................................................................................... 28
4.12 OSD.......................................................................................................................................... 28
4.12.1 On-Chip OSD SRAM................................................................................................. 28
4.12.2 Color Look-up Table (LUT)....................................................................................... 29
4.13 On-Chip Microcontroller (OCM)............................................................................................. 30
4.13.1 Standalone Configuration........................................................................................... 30
4.13.2 Full-Custom Configuration ........................................................................................ 31
4.13.3 In-System-Programming (ISP) of FLASH ROM Devices ......................................... 32
4.13.4 UART Interface .......................................................................................................... 33
4.13.5 DDC2Bi Interface....................................................................................................... 33
4.13.6 General Purpose Inputs and Outputs (GPIO’s) .......................................................... 33
4.14 Bootstrap Configuration Pins................................................................................................... 34
4.15 Host Interface........................................................................................................................... 35
4.15.1 Host Interface Command Format ............................................................................... 35
4.15.2 2-wire Serial Protocol................................................................................................. 36
4.16 Miscellaneous Functions.......................................................................................................... 37
4.16.1 Low Power State......................................................................................................... 37
4.16.2 Pulse Width Modulation (PWM) Back Light Control................................................ 37
5. Electrical Specifications ................................................................................................................... 38
5.1 Preliminary DC Characteristics ................................................................................................. 38
5.2 Preliminary AC Characteristics ................................................................................................. 40
6. Ordering Information ....................................................................................................................... 41
7. Mechanical Specifications................................................................................................................ 42
June 2002
iv C2120-DAT-01C

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*** Genesis Microchip Confidential ***
gm2110/20 Preliminary Data Sheet
3. GM2110/20 PIN LIST
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Pin Name
AVDD_RED
RED+
RED-
AGND_RED
AVDD_GREEN
GREEN+
GREEN-
AGND_GREEN
AVDD_BLUE
BLUE+
BLUE-
AGND_BLUE
AVDD_ADC
ADC_TEST
AGND_ADC
SGND_ADC
GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
HSYNC
VSYNC
No.
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
137
136
Table 1. Analog Input Port
I/O Description
AP Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
AI Positive analog input for Red channel.
AI Negative analog input for Red channel.
AG Analog ground for the red channel.
Must be directly connected to the analog system ground plane.
AP Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
AI Positive analog input for Green channel.
AI Negative analog input for Green channel.
AG Analog ground for the green channel.
Must be directly connected to the analog system ground plane.
AP Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
AI Positive analog input for Blue channel.
AI Negative analog input for Blue channel.
AG Analog ground for the blue channel.
Must be directly connected to the analog system ground plane.
AP Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
AO Analog test output for ADC Do not connect.
AG Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.
AG Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the analog system ground plane.
G Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane
P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
G Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane.
P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
I ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
I ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Pin Name
AVDD_RPLL
AVSS_RPLL
TCLK
XTAL
VDD_RPLL
VSS_RPLL
Table 2. RCLK PLL Pins
No I/O Description
150 AP
149 AG
152 AI
151 AO
148 P
147 G
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-
ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 13.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
June 2002
4 C2120-DAT-01C

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