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PDF V58C2512SB Datasheet ( Hoja de datos )

Número de pieza V58C2512SB
Descripción High Performance 512M-Bit DDR SDRAM
Fabricantes ProMOS Technologies 
Logotipo ProMOS Technologies Logotipo
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V58C2512SB datasheet

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V58C2512SB pdf
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ProMOS TECHNOLOGIES
V58C2512(804/404/164)SB
Block Diagram
64M x 8
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 2048
Row decoder
Memory array
Bank 1
8192 x 2048
Row decoder
Memory array
Bank 2
8192 x 2048
Row decoder
Memory array
Bank 3
8192 x 2048
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ7
Data Strobe
Control logic & timing generator
V58C2512(804/404/164)SB Rev. 1.4 March 2007
5

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V58C2512SB arduino
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ProMOS TECHNOLOGIES
V58C2512(804/404/164)SB
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a ProMOS specific test mode
during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to
the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1 BA 0
A12 to A3
A2 A1 A0 Address Bus
0 MRS
RFU : Must be set "0"
0 I/O DLL Extended Mode Register
0 MRS
RFU
DLL TM CAS Latency BT Burst Length
Mode Register
A8 DLL Reset A7 mode
0 No
0 Normal
1 Yes
1 Test
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
Burst Length
BA0
An ~ A0
0 (Existing)MRS Cycle
A6 A5 A4 Latency
0 0 0 Reserve
A2 A1 A0
1 Extended Funtions(EMRS)
0 0 1 Reserve
000
01 0
2
001
01 1
3
010
1 0 0 Reserve
011
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
10
11
11
1 Reserve
0 2.5
1 Reserve
100
101
110
111
A1 I/O Strength
0 Full
1 Half
A0
0
1
Latency
Sequential Interleave
Reserve
Reserve
22
44
88
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
DLL Enable
Enable
Disable
Mode Register Set
012345678
CK, CK
Command
Precharge
All Banks
tCK
tRP *2
*1
Mode
Register Set
tMRD
Any
Command
V58C2512(804/404/164)SB Rev. 1.4 March 2007
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