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PDF FBGA-SD Data sheet ( Hoja de datos )

Número de pieza FBGA-SD
Descripción Fine Pitch Ball Grid Array
Fabricantes STATS ChipPAC 
Logotipo STATS ChipPAC Logotipo



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No Preview Available ! FBGA-SD Hoja de datos, Descripción, Manual

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FBGA-SD
Fine Pitch Ball Grid Array - Stacked Die
• FBGA-SD: Laminate substrate based enabling
2 & 4 layers of routing flexibility
• FBGA-T-SD: Single metal layer tape based
substrate with dense routing & good electrical
performance
• Available in 1.4mm (LFBGA-SD), 1.2mm (TFBGA-
SD/TFBGA-T-SD), 1.0mm (VFBGA-SD/VFBGA-T-
SD) & 0.80mm (WFBGA-SD) maximum package
thickness
• Stacking of die allows for more functionality in
an array molded, cost effective, space saving
package solution
FEATURES
• 2 die to 7 die stack with spacer capability
• 5 x 5mm to 23 x 23mm body size
• Package height at 1.0, 1.2, 1.4 and 1.7mm max.
• Flexible die stacking options (“pyramid,” “same die,” etc.)
• 0.5mm to 1.0mm ball pitch, Eutectic and Lead-free
solder ball
• Flash/SRAM/PSRAM/Logic/Analog combinations
• JEDEC standard package outlines
• Die thinning to 75um (3mils) capability
• Low loop wire bonding; reverse and die to die
• Up to 2mm die overhang per side
• Halogen-free and Low-K wafer compatible BOM
• Ball counts up to 450 balls
APPLICATIONS
• Suitable for a variety of applications including
memory integration (ASIC or Logic)
• Chipset integration (Analog/Digital), mixed
technologies integration (Baseband/RF)
• Handheld products (Cellular Phones, Pagers, MP3
Players, GPS)
• Consumer electronics (Internet applications,
Digital Cameras/Camcorders)
• Computers (Network PCs)
• PC peripherals (Disk Drivers, DC-R/RW, Mini Disk,
DVD Drivers)
DESCRIPTION
STATS ChipPAC’s Fine Pitch Ball Grid Array Stacked Die
(FBGA-SD) offering includes LFBGA-SD, TFBGA-SD,
VFBGA-SD and WFBGA-SD packages. Tape versions of
VFBGA-SD and TFBGA-SD are also available. STATS
ChipPAC’s chip stack technology offers the flexibility of
stacking 2 to 7 die in a single package. Die to die bonding
capability enables device and signal integration to
improve electrical performance and reduce overall
package I/O requirements. Wafer thinning technology,
overhang wire bond technology and the use of spacers
between stacked die provide the flexibility to stack almost
any desirable configuration of die in one package. This
capability uses existing assembly infrastructure, which
results in more functional integration with lower overall
package cost. The use of the latest packaging materials
allows this package to meet JEDEC Moisture Resistance
Test Level 2a with Lead-free reflow conditions. This is an
ideal package for cell phone applications where Digital,
Flash, SRAM, PSRAM and Logic are stacked into a single
package.
www.statschippac.com

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