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PDF K4D263238I-VC Data sheet ( Hoja de datos )
| Número de pieza | K4D263238I-VC | |
| Descripción | 128M-Bit GDDR SDRAM | |
| Fabricantes | Samsung Electronics | |
| Logotipo |  |
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K4D263238I-VC
128M GDDR SDRAM
128Mbit GDDR SDRAM
Revision 1.3
November 2006
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.3 November 2006
1 page  
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K4D263238I-VC
128M GDDR SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ′s and DM′s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS
Input/Output
Data input and output are synchronized with both edge of DQS.
DM0 ~ DM3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
MCL
Must Connect Low
Must connect Low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.3 November 2006
5 Page 
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K4D263238I-VC
IBIS : Pull down
Voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Pulldown Current(mA)
100% Min 100% Max
00
6.984
9.1795
13.86
17.193
20.448
25.036
26.82
32.714
32.832
40.205
38.484
47.487
43.632
54.538
48.384
61.347
52.56
67.881
56.088
74.129
58.896
80.058
61.02
85.635
62.604
90.816
63.756
95.568
64.548
99.825
65.124
103.532
65.628
106.579
65.988
108.922
66.312
110.66
66.6
112.002
66.816
112.992
67.068
113.762
67.284
114.422
67.464
115.082
67.608
115.632
67.824
116.072
67.968
116.512
128M GDDR SDRAM
Pulldown Current(mA)
60% Min 60% Max
00
6.048
8.624
12.132
17.16
17.748
25.388
23.256
33.616
28.476
41.404
33.336
49.104
37.908
56.628
41.976
63.492
45.432
70.18
48.348
76.208
50.688
81.532
52.452
86.196
53.748
90.2
54.684
93.841
55.332
96.481
55.8
98.34
56.232
99.077
56.52
100.177
56.808 100.782
57.06
101.167
57.312 101.552
57.456 101.739
57.636 102.245
57.852 102.553
58.032 102.828
58.176 102.861
58.32
102.905
Pulldown Current(mA)
30% Min 30% Max
00
3.708
5.28
7.38
10.56
10.836 15.532
14.076 20.68
17.172
25.3
19.944 30.096
22.5
34.408
24.624
38.5
26.424 42.196
27.828 45.452
28.908 48.18
29.664 50.468
30.24 52.228
30.672 53.548
30.924 54.604
31.212 55.352
31.356 55.924
31.536 56.32
31.68 56.628
31.824 56.892
31.932 57.156
32.076 57.376
32.184 57.508
32.292 57.728
32.364 57.816
32.436 57.992
32.58 58.124
Pull down
140
120
100 100% Min
100% Max
80 60% Min
60 60% Max
30% Min
40 30% Max
20
0
Voltage (V)
- 11 -
Rev. 1.3 November 2006
11 Page | ||
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