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PDF DP8392C Data sheet ( Hoja de datos )
| Número de pieza | DP8392C | |
| Descripción | CTI Coaxial Transceiver Interface | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1995
DP8392C DP8392C-1 CTI
Coaxial Transceiver Interface
General Description
The DP8392C Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
Features
Y Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Y Integrates all transceiver electronics except signal
power isolation
Y Innovative design minimizes external component count
Y Jabber timer function integrated on chip
Y Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Y Precision circuitry implements receive mode collision
detection
Y Squelch circuitry at all inputs rejects noise
Y Designed for rigorous reliability requirements of
IEEE 802 3
Y Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1 Receiver Functions
3 2 Transmitter Functions
3 3 Collision Functions
3 4 Jabber Functions
4 0 Typical Applications
5 0 Connection Diagrams
6 0 Pin Descriptions
7 0 Absolute Maximum Ratings
8 0 DP8392C Electrical Characteristics
9 0 DP8392C-1 Electrical Characteristics
10 0 Switching Characteristics
11 0 Timing and Load Diagram
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
TL F 11085 – 1
C1995 National Semiconductor Corporation TL F 11085
RRD-B30M115 Printed in U S A
1 page  
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6 0 Pin Descriptions
28-Pin PLCC 16-Pin DIP Name I O
Description
2 1 CDa O Collision Output Balanced differential line driver outputs from the collision detect
3
2 CDb
circuitry The 10 MHz signal from the internal oscillator is transferred to these
outputs in the event of collision excessive transmission (jabber) or during CD
Heartbeat condition These outputs are open emitters pulldown resistors to VEE
are required When operating into a 78X transmission line these resistors should
be 500X In Cheapernet applications where the 78X drop cable is not used
higher resistor values (up to 1 5k) may be used to save power
4 3 RXa O Receive Output Balanced differential line driver outputs from the Receiver These
12
6 RXb
outputs also require 500X pulldown resistors
13
7
TXa
I Transmit Input Balanced differential line receiver inputs to the Transmitter The
14
8 TXb
common mode voltage for these inputs is determined internally and must not be
externally established Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO
15
9
HBE
I Heartbeat Enable This input enables CD Heartbeat when grounded disables it
when connected to VEE
18
11
RRa
I External Resistor A fixed 1k 1% resistor connected between these pins
19
12 RRb
establishes internal operating currents
26 14 RXI I Receive Input Connects directly to the coaxial cable Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion amplified and
outputted at RXg
28
15
TXO
O Transmit Output Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable
1
16
CDS
I Collision Detect Sense Ground sense connection for the collision detect circuit
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold
16 17
10 GND
Positive Supply Pin A 0 1 mF ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible
5 – 11
20 – 25
4 VEE
5
13
Negative Supply Pins In order to make full use of the 3 5W power dissipation
capability of this package these pins should be connected to a large metal frame
area on the PC board Doing this will reduce the operating die temperature of the
device thereby increasing the long term reliability
IEEE names for CDg e CIg RXg e DIg TXg e DOg
6 1 P C BOARD LAYOUT
The DP8392C package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802 3 standard In
order to fully utilize this heat dissipation design the three
VEE pins are to be connected to a copper plane which
should be included in the printed circuit board layout
There are two basic considerations in designing a PCB for
the DP8392C and C-1 CTI The first is ensuring that the
layout does not degrade the electrical characteristics of the
DP8392 and enables the end product to meet the IEEE
802 3 specifications The second consideration is meeting
the thermal requirements to the DP8392
Since the DP8392 is highly integrated the layout is actually
quite simple and there are just a few guidelines
1 Ensure that the parasitic capacitance added to the RXI
and TXO pins is minimized To do this keep these signal
traces short and remove any power planes under these
signals and under any components that connect to these
signals Figure 6 shows the component placement for the
DIP package The PLCC component placement would be
similar as shown in Figure 7
2 The power supply layout to the CTI should be relatively
clean Usually the CTI’s power is supplied directly by a
DC-DC converter The power should be routed either
through separate isolated planes or via thick PCB traces
For the second consideration the packaged DP8392 must
have a thermal resistance of 40 C –45 C W to meet the full
0 C –70 C temperature range The CTI dissipates more
power when transmitting than while it is idle In order to do
this the thermal resistance of the device must be 40 C –
45 C W To meet this requirement during transmission it is
recommended that a small printed circuit board plane be
connected to all VEE pins on the solder side of the PCB
The size of the trace plane depends on the package used
and the duty cycle of transmissions For the DIP package
the plane should be connected to pins 4 – 5 13 and the size
should be approximately 0 2 square inches for applications
where the duty cycle of the transmitter is very low (k10%)
This would be typical of adapter or motherboard applica-
tions In applications where the transmitter duty cycle may
be large (repeaters and external transceivers) the total area
should be increased to 0 4 in2 Figure 6 illustrates a recom-
mended component side layout for these planes
5
5 Page 
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12 0 Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number DP8392CN or DP8392CN-1
NS Package Number N16E
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DP8392C.PDF ] | |
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