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Número de pieza | K4S280832I | |
Descripción | (K4S28xx32I) JEDEC standard 3.3V power supply LVTTL compatible | |
Fabricantes | Samsung Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de K4S280832I (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! K4S280432I
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K4S281632I
Synchronous DRAM
128Mb I-die SDRAM Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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1 page K4S280432I
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K4S281632I
FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
Data Input Register
CLK
ADD
Bank Select
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Column Decoder
LCKE
LRAS LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
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K4S281632I
Synchronous DRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
CAS latency=2
Output data
hold time
CAS latency=3
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
50
Min Max
5
1000
-
- 4.5
--
2-
--
2-
2-
1.5 -
1-
1-
- 4.5
--
60 (x16 only)
Min Max
6
1000
-
5
-
2.5
-
2.5
2.5
1.5
1
1
5
-
75
Min Max
7.5
1000
10
5.4
6
3
3
2.5
2.5
1.5
0.8
1
5.4
6
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time
tSH applies for address holde time, clock enable hold time, commend hold time and data hold time
Unit Note
ns 1
ns 1,2
ns 2
ns 3
ns 3
ns 3,4
ns 3,4
ns 2
ns
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Output fall time
Output rise time
Output fall time
Symbol
trh
tfh
trh
tfh
Condition
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Min
1.37
1.30
2.8
2.0
Typ
3.9
2.9
Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
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Rev. 1.1 May 2006
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet K4S280832I.PDF ] |
Número de pieza | Descripción | Fabricantes |
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K4S280832C | 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL | Samsung semiconductor |
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