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PDF X20CZ16 Data sheet ( Hoja de datos )
| Número de pieza | X20CZ16 | |
| Descripción | High Speed NOVRAM | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X20CZ16 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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www.DataSheet4U.com
APPLICATION NOTE
A V A I LABLE
AN56
High Speed NOVRAM
X20CZ16
FEATURES
• Fast access time: 35ns
• High reliability
—Endurance: 105 nonvolatile store operations
—Retention: 10 years minimum
• Power-on recall
—EEPROM data automatically recalled into RAM
upon power-up
• Low power CMOS
—Standby: 1mA
• Infinite EEPROM array recall, and RAM read and
write cycles
• Hardware store initiation (store cycle time < 10ms)
• Available in the 32-lead plastic leadless chip
carrier package
DESCRIPTION
The Xicor X20CZ16 is a 2K x 8 NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile electrically erasable PROM (EEPROM). The
X20CZ16 is fabricated with advanced CMOS floating
gate technology to achieve high speed with low power
and wide power-supply margin.
The NOVRAM design allows data to be easily trans-
ferred from RAM to EEPROM (store) and EEPROM to
RAM (recall). The store operation is completed in
10ms or less and the recall operation is completed in
20µs or less. An automatic array recall operation
reloads the contents of the EEPROM into RAM upon
power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 100,000 store operations to
the EEPROM. Data retention is specified to be greater
than 10 years.
FUNCTIONAL DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
EEPROM
Array
SRAM
Array
VCC
VSS
DQ0
DQ1 Data I/O Store/
DQ2
Recall
Control
VCC
DQ3
DQ4
DQ5
DQ6 OE
DQ7 NE
Read/Write/
Store Logic
CE
WE
REV 1.4.2 10/3/03
www.xicor.com
Characteristics subject to change without notice. 1 of 14
1 page  
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X20CZ16
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
Symbol
tRC(3)
tCE
tAA
tOE
tLZ(3)
tOLZ(3)
tHZ(3)
tOHZ(3)
tOH(3)
Parameter
Read cycle time
Chip enable access time
Address access time
Output enable access time
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
X20CZ16-35
–40 to +85°C
Min.
Max.
35
35
35
20
5
0
0 15
0 15
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: (3) These parameters are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
Address
CE
OE
tRC
tCE
tOE
WE
Data I/O
tOLZ
tLZ
Data Valid
tOH
tAA
tHZ
Data Valid
tOHZ
REV 1.4.2 10/3/03
www.xicor.com
Characteristics subject to change without notice. 5 of 14
5 Page 
www.DataSheet4U.com
X20CZ16
DETAILED PIN DESCRIPTIONS
Addresses (A0–A10)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Out-
put Enable LOW disables a store operation regardless
of the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20CZ16 through
the I/O pins. The I/O pins are placed in the high imped-
ance state when either CE or OE is HIGH or when NE is
LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
the static RAM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the store and
recall function to the EEPROM array.
DEVICE OPERATION
The X20CZ16 has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE pin. In SRAM mode, the memory oper-
ates as a standard fast static RAM. In nonvolatile
mode, data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
SRAM Read
The X20CZ16 performs a READ cycle whenever CE
and OE are LOW while WE and NE are HIGH. The
address specified on pads A0–A10 determines which
of the 2048 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of tRC. If the READ is initiated
by CE or OE, the outputs will be valid at tCE or at tOE,
whichever is later. The data outputs will repeatedly
respond to address changes within the tRC access
time without the need for transition on any control input
pins, and will remain valid until another address
change or until CE or OE is brought HIGH or WE or NE
is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are
LOW and NE is HIGH. The address inputs must be sta-
ble prior to entering the WRITE cycle and must remain
stable until either CE or WE goes HIGH at the end of
the cycle. The data on pins DQ0–7 will be written into
the memory if it is valid tDW before the end of a WE
controlled WRITE or tDW before the end of a CE con-
trolled WRITE.
It is recommended that OE is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If OE is left LOW, internal circuitry
will turn off the output buffers tWZ after WE goes LOW.
Noise Consideration
The X20CZ16 is a high speed memory and therefore
must have a high frequency bypass capacitor of
approximately 0.1 µF connected between VCC and VSS
using leads and traces that are as short as possible.
As with all high speed CMOS ICs, normal careful rout-
ing of power, ground and signals will help prevent
noise problems.
Hardware Nonvolatile STORE
A STORE cycle is performed when NE , CE and WE
are LOW while OE is HIGH. While any sequence to
achieve this state will initiate a STORE, only WE
initiation and CE initiation are practical without risking
an unintentional SRAM WRITE that would disturb
SRAM data. During a STORE cycle, previous
nonvolatile data is erased the SRAM contents are then
programmed into nonvolatile elements. Once a
STORE cycle is initiated, further input and output is
disabled and the DQ0–7 pins are tristated until the
cycle is completed.
REV 1.4.2 10/3/03
www.xicor.com
Characteristics subject to change without notice. 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet X20CZ16.PDF ] | |
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