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PDF ICS43004I-04 Data sheet ( Hoja de datos )
| Número de pieza | ICS43004I-04 | |
| Descripción | FEMTOCLOCKS-TM CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843004I-04 is a 4 output LVPECL
ICS Synthesizer optimized to generate clock
HiPerClockS™ frequencies for a variety of high performance
applications and is a member of the
HiPerClocksTM family of high performance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS843004I-04 uses ICS’ 3rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter. This
ensures that it will easily meet clocking requirements
for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/
OC12/OC-48). This device is suitable for multi-rate and
multiple port line card applications. The ICS843004I-04
is conveniently packaged in a small 24-pin TSSOP
package.
FEATURES
• Four LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.82ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.94ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
XTAL_IN
OSC
XTAL_OUT
CLK Pulldown
INPUT_SEL Pulldown
0
1
MR Pulldown
F_SEL0 Pullup
F_SEL1 Pullup
Phase
Detector
VCO
M = ÷32
÷1
÷4
F_SEL2 Pullup
F_SEL3 Pullup
0 Q0
nQ0
1
0 Q1
1 nQ1
0 Q2
1 nQ2
0 Q3
1 nQ3
843004AGI-04
www.icst.com/products/hiperclocks.html
1
PIN ASSIGNMENT
nQ1
Q1
VCCo
Q0
nQ0
MR
F_SEL3
nc
VCCA
F_SEL0
VCC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
2 2 VCCO
21 Q3
20 nQ3
19 VEE
18 F_SEL2
17 INPUT_SEL
16 CLK
15 VEE
14 XTAL_IN
13 XTAL_OUT
ICS843004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REV. A FEBRUARY 15, 2006
1 page  
Integrated
Circuit
Systems, Inc.
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCCA = 2V
VCC,
VCCO
LVPECL
VEE
SCOPE
Qx
nQx
-1.3V±0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQx
Qx
nQy
Qy
t sk(o)
OUTPUT SKEW
Phase Noise Mask
f1 Offset Frequency f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Clock
20%
Outputs
80%
tR
RMS PHASE JITTER
OUTPUT RISE/FALLTIME
80%
tF
VSW I N G
20%
nQ0:nQ3
Q0:Q3
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843004AGI-04
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 15, 2006
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CC_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CC_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
– (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX
OH_MAX
L
CC_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX
OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843004AGI-04
www.icst.com/products/hiperclocks.html
11
REV. A FEBRUARY 15, 2006
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS43004I-04.PDF ] | |
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