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PDF K9LAG08U0M Data sheet ( Hoja de datos )

Número de pieza K9LAG08U0M
Descripción Flash Memory
Fabricantes Samsung Electronics 
Logotipo Samsung Electronics Logotipo



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K9HBG08U1M
K9LAG08U0M K9MCG08U5M
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FLASH MEMORY
K9XXG08UXM
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K9LAG08U0M pdf
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K9HBG08U1M
K9LAG08U0M K9MCG08U5M
PIN CONFIGURATION (TSOP1)
K9HBG08U1M-PCB0/PIB0
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FLASH MEMORY
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8°
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
#25
1.00±0.05
0.039±0.002
01..02407MAX
0.02
0.002
MIN
(
0.50
0.020
)
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K9LAG08U0M arduino
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K9HBG08U1M
K9LAG08U0M K9MCG08U5M
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FLASH MEMORY
Memory Map
K9LAG08U0M is arranged in four 4Gb memory planes. Each plane contains 2,048 blocks and 2112 byte page registers. This allows it
to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that two-plane program/erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3
separately.
For example, two-plane program/erase operation into plane 0 and plane 2 is prohibited. that is to say, two-plane program/erase oper-
ation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed
Plane 0
(2048 Block)
Block 0
Page 0
Page 1
Page 126
Page 127
Block 2
Page 0
Page 1
Page 126
Page 127
Plane 1
(2048 Block)
Block 1
Page 0
Page 1
Page 126
Page 127
Block 3
Page 0
Page 1
Page 126
Page 127
Plane 2
(2048 Block)
Block 4096
Page 0
Page 1
Page 126
Page 127
Block 2050
Page 0
Page 1
Page 126
Page 127
Plane 3
(2048 Block)
Block 4097
Page 0
Page 1
Page 126
Page 127
Block 2051
Page 0
Page 1
Page 126
Page 127
Block 4092
Page 0
Page 1
Page 126
Page 127
Block 4094
Page 0
Page 1
Page 126
Page 127
2112byte Page Registers
Block 4093
Page 0
Page 1
Page 126
Page 127
Block 4095
Page 0
Page 1
Page 126
Page 127
2112byte Page Registers
Block 8188
Page 0
Page 1
Page 126
Page 127
Block 8190
Page 0
Page 1
Page 126
Page 127
2112byte Page Registers
Block 8189
Page 0
Page 1
Page 126
Page 127
Block 8191
Page 0
Page 1
Page 126
Page 127
2112byte Page Registers
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