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PDF EP2C5Q208I7N Data sheet ( Hoja de datos )

Número de pieza EP2C5Q208I7N
Descripción Cyclon II Device
Fabricantes Altera 
Logotipo Altera Logotipo



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Cyclone II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
CII5V1-3.1

1 page




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Contents
Cyclone II Clock Timing Parameters ........................................................................................... 5–22
Clock Network Skew Adders ....................................................................................................... 5–28
IOE Programmable Delay ............................................................................................................. 5–29
Default Capacitive Loading of Different I/O Standards .......................................................... 5–30
I/O Delays ....................................................................................................................................... 5–31
Maximum Input & Output Clock Rate ....................................................................................... 5–43
High Speed I/O Timing Specifications ....................................................................................... 5–52
External Memory Interface Specifications .................................................................................. 5–60
JTAG Timing Specifications .......................................................................................................... 5–61
PLL Timing Specifications ............................................................................................................ 5–63
Duty Cycle Distortion ......................................................................................................................... 5–64
DCD Measurement Techniques ................................................................................................... 5–65
Document Revision History ............................................................................................................... 5–71
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Document Revision History ................................................................................................................. 6–2
Section II. Clock Management
Revision History .................................................................................................................................... 6–1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2
PLL Reference Clock Generation ................................................................................................... 7–6
Clock Feedback Modes ....................................................................................................................... 7–10
Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Source-Synchronous Mode ........................................................................................................... 7–13
Hardware Features .............................................................................................................................. 7–14
Clock Multiplication & Division .................................................................................................. 7–14
Programmable Duty Cycle ........................................................................................................... 7–15
Phase-Shifting Implementation .................................................................................................... 7–16
Control Signals ................................................................................................................................ 7–17
Manual Clock Switchover ............................................................................................................. 7–20
Clocking ................................................................................................................................................ 7–21
Global Clock Network ................................................................................................................... 7–21
Clock Control Block ....................................................................................................................... 7–24
Global Clock Network Clock Source Generation ...................................................................... 7–26
Global Clock Network Power Down ........................................................................................... 7–28
clkena signals .................................................................................................................................. 7–29
Board Layout ........................................................................................................................................ 7–30
Altera Corporation
v
Cyclone II Device Handbook, Volume 1

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EP2C5Q208I7N arduino
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Chapter Revision Dates
The chapters in this book, Cyclone II Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised:
February 2007
Part number: CII51001-3.1
Chapter 2. Cyclone II Architecture
Revised:
February 2007
Part number: CII51002-3.1
Chapter 3. Configuration & Testing
Revised:
February 2007
Part number: CII51003-2.2
Chapter 4. Hot Socketing & Power-On Reset
Revised:
February 2007
Part number: CII51004-3.1
Chapter 5. DC Characteristics & Timing Specifications
Revised:
February 2007
Part number: CII51005-3.1
Chapter 6. Reference & Ordering Information
Revised:
February 2007
Part number: CII51006-1.4
Chapter 7. PLLs in Cyclone II Devices
Revised:
February 2007
Part number: CII51007-3.1
Chapter 8. Cyclone II Memory Blocks
Revised:
February 2007
Part number: CII51008-2.3
Chapter 9. External Memory Interfaces
Revised:
February 2007
Part number: CII51009-3.1
Altera Corporation
xi

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