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PDF KM6161000B Data sheet ( Hoja de datos )

Número de pieza KM6161000B
Descripción 64K X 16-Bit Low Power CMOS Static RAM
Fabricantes Samsung Electronics 
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No Preview Available ! KM6161000B Hoja de datos, Descripción, Manual

KM6161000B Family
Document Title
64K x16 bit Low Power CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft
1.0 Finalize
- One datasheet for commercial and industrial part.
2.0 Revised
- Change datasheet format.
- Remove Icc write current value.
- Remove low power product from product
CMOS SRAM
Draft Data
August 12, 1995
April 15, 1996
Remark
Preliminary
Final
February 12, 1998 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 2.0
February 1998

1 page




KM6161000B pdf
KM6161000B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL=30pF+1TTL
AC CHARACTERISTICS
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB,LB Access Time
Chip select to low-Z output
UB,LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB,LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
UB, LB valid to end of write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tBW
tWR
tWHZ
tDW
tDH
tOW
CL1)
1. Including scope and jig capacitance
55ns
Min Max
55 -
- 55
- 55
- 25
- 25
10 -
5-
5-
0 20
0 20
0 20
10 -
55 -
45 -
0-
45 -
40 -
45 -
0-
0 25
25 -
0-
5-
Speed Bins
70ns
Min Max
70 -
- 70
- 70
- 35
- 35
10 -
5-
5-
0 25
0 25
0 25
15 -
70 -
60 -
0-
60 -
50 -
60 -
0-
0 30
30 -
0-
5-
100ns
Min Max
100 -
- 100
- 100
- 50
- 50
10 -
5-
5-
0 30
0 30
0 30
15 -
100 -
80 -
0-
80 -
70 -
80 -
0-
0 35
40 -
0-
5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
VCC for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CSVcc-0.2V
VCC=3.0V, CSVcc-0.2V
See data retention waveform
Min Typ Max Unit
2.0 - 5.5 V
- - 15 µA
0- -
ms
5- -
5 Revision 2.0
February 1998

5 Page










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