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PDF M464S0924DTS Data sheet ( Hoja de datos )
| Número de pieza | M464S0924DTS | |
| Descripción | 8Mx64 SDRAM SODIMM based on 8Mx16 | |
| Fabricantes | Samsung semiconductor | |
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M464S0924DTS
PC133/PC100 SODIMM
M464S0924DTS SDRAM SODIMM
8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M464S0924DTS is a 8M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M464S0924DTS consists of four CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and
a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-
epoxy substrate. Three 0.1uF decoupling capacitors are
mounted on the printed circuit board in parallel for each
SDRAM. The M464S0924DTS is a Small Outline Dual In-line
Memory Module and is intended for mounting into 144-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
FEATURE
• Performance range
Part No.
M464S0924DTS-L7C/C7C
M464S0924DTS-L7A/C7A
M464S0924DTS-L1H/C1H
M464S0924DTS-L1L/C1L
Max Freq. (Speed)
133MHz (7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,000mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 VSS 2
3 DQ0 4
5 DQ1 6
7 DQ2 8
9 DQ3 10
11 VDD 12
13 DQ4 14
15 DQ5 16
17 DQ6 18
19 DQ7 20
21 VSS 22
23 DQM0 24
25 DQM1 26
27 VDD 28
29 A0 30
31 A1 32
33 A2 34
35 VSS 36
37 DQ8 38
39 DQ9 40
41 DQ10 42
43 DQ11 44
45 VDD 46
47 DQ12 48
49 DQ13 50
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
51 DQ14 52 DQ46 95 DQ21 96 DQ53
53 DQ15 54 DQ47 97 DQ22 98 DQ54
55 VSS 56 VSS 99 DQ23 100 DQ55
57 NC 58 NC 101 VDD 102 VDD
59 NC 60 NC 103 A6 104 A7
Voltage Key
105 A8 106 BA0
107 V SS 108 V SS
109 A9 110 BA1
61 CLK0 62 CKE0 111 A10/AP 112 A11
63 VDD 64 VDD 113 VDD 114 VDD
65 RAS 66 CAS 115 DQM2 116 DQM6
67 W E 68 *CKE1 117 DQM3 118 DQM7
69 CS0 70 *A12 119 V SS 120 V SS
71 *CS1 72 *A13 121 DQ24 122 DQ56
73 DU 74 *CLK1 123 DQ25 124 DQ57
75 VSS 76 VSS 125 DQ26 126 DQ58
77 NC 78 NC 127 DQ27 128 DQ59
79 NC 80 NC 129 VDD 130 VDD
81 VDD 82 VDD 131 DQ28 132 DQ60
83 DQ16 84 DQ48 133 DQ29 134 DQ61
85 DQ17 86 DQ49 135 DQ30 136 DQ62
87 DQ18 88 DQ50 137 DQ31 138 DQ63
89 DQ19 90 DQ51 139 V SS 140 V SS
91 VSS 92 VSS 141 **SDA 142 **SCL
93 DQ20 94 DQ52 143 VDD 144 VDD
PIN NAMES
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CLK0
CKE0
CS0
RAS
CAS
WE
DQM0 ~ 7
VDD
VSS
SDA
SCL
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address storbe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Serial data I/O
Serial clock
Don′t use
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
1 page  
M464S0924DTS
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)
Parameter
Sym-
bol
Test Condition
Operating current
(One bank active)
ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Precharge standby current
in power-down mode
ICC2P CKE ≤ V IL(max), tCC = 10ns
ICC2PS CKE & CLK ≤ V IL(max), tCC = ∞
Precharge standby current
in non power-down mode
ICC2N
ICC2NS
CKE ≥ V I H(min), CS ≥ VIH (min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ V I H(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
Active standby current in
power-down mode
ICC3P
IC C 3PS
CKE ≤ V IL(max), tCC = 10ns
CKE & CLK ≤ V IL(max), tCC = ∞
Active standby current in
non power-down mode
(One bank active)
CKE ≥ V I H(min), CS ≥ VIH (min), tCC = 10ns
ICC3N Input signals are changed one time during 20ns
CKE ≥ V I H(min), CLK ≤ VIL(max), tCC =∞
ICC3NS Input signals are stable
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
Refresh current
ICC5 tRC ≥ tRC(min)
Self refresh current
ICC6 CKE ≤ 0.2V
C
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
PC133/PC100 SODIMM
Version
Unit Note
-7C -7A -1H -1L
440 400 400 400 mA
1
8
mA
8
80
mA
40
20
mA
20
120 mA
100 mA
560 560 520 520 mA
1
880 800 760 760 mA
8 mA
3.2 mA
2
Rev. 0.1 Sept. 2001
5 Page 
M464S0924DTS
PC133/PC100 SODIMM
Byte #
Function Described
35 Data signal input hold time
36~61 Superset information (maybe used in future)
62 SPD data revision code
63 Checksum for bytes 0 ~ 62
64 Manufacturer JEDEC ID code
65~71 ...... Manufacturer JEDEC ID code
72 Manufacturing location
73 Manufacturer part # (Memory module)
74 Manufacturer part # (DIMM Configuration)
75 Manufacturer part # (Data bits)
76 ...... Manufacturer part # (Data bits)
77 ...... Manufacturer part # (Data bits)
78 Manufacturer part # (Mode & operating voltage)
79 Manufacturer part # (Module depth)
80 ...... Manufacturer part # (Module depth)
81 Manufacturer part # (Refresh, #of banks in Comp. & Interface)
82 Manufacturer part # (Composition component)
83 Manufacturer part # (Component revision)
84 Manufacturer part # (Package type)
85 Manufacturer part # (PCB revision & type)
86 Manufacturer part # (Hyphen)
87 Manufacturer part # (Power)
88 Manufacturer part # (Minimum cycle time)
89 Manufacturer part # (Minimum cycle time)
90 Manufacturer part # (TBD)
91 Manufacturer revision code (For PCB)
92 ...... Manufacturer revision code (For component)
93 Manufacturing date (Year)
94 Manufacturing date (Week)
95~98 Assembly serial #
99~125 Manufacturer specific data (may be used in future)
126 System frequency for 100MHz
127 PC100 specification details
128+ Unused storage locations
Function Supported
-7C -7A -1H -1L
0.8ns 0.8ns 10ns 10ns
-
Intel Rev 1.2B
-
Samsung
Samsung
Onyang Korea
M
4
Blank
6
4
S
0
9
2
4
D
T
S
"-"
L/C
7 71 1
CAH L
Blank
S
D-die (5th Gen.)
-
-
-
Undefined
100MHz
Detailed PC100 Information
Undefined
-7C
08h
65h
37h
43h
8Fh
Hex value
-7A -1H
08h 10h
00h
12h
A6h 0Dh
CEh
00h
01h
4Dh
34h
20h
36h
34h
53h
30h
39h
32h
34h
44h
54h
53h
2Dh
4Ch / 43h
37h 31h
41h 48h
20h
53h
44h
-
-
-
-
64h
8Fh 8Fh
-
Note
-1L
10h
3Dh
31h
4Ch
3
3
4
8Dh
Note : 1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
Rev. 0.1 Sept. 2001
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M464S0924DTS.PDF ] | |
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