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PDF KS57P0408 Data sheet ( Hoja de datos )
| Número de pieza | KS57P0408 | |
| Descripción | (KS57x040x) single-chip CMOS microcontroller | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KS57C0404/C0408/P0408 MICROCONTROLLER
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
The KS57C0404/C0408 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The KS57P0408 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to KS57C0404/C0408.
With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
KS57C0404/C0408 offers an excellent design solution for a wide variety of general-purpose applications.
Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the KS57C0404/C0408's advanced CMOS technology provides for low power consumption and a
wide operating voltage range.
1–1
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KS57C0404/C0408/P0408 MICROCONTROLLER
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C SC2 SC1 SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
KS57C0404/C0408 using an external clock source, the external clock signal should be input to Xin, and its
inverted signal to Xout.
A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds of
3.91 milliseconds at 4.19MHz. The following components support interrupt processing:
Interrupt enable flags
Interrupt request flags
Interrupt priority registers
Power-down termination circuit
1–5
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KS57C0404/C0408/P0408 MICROCONTROLLER
PRODUCT OVERVIEW
Table 1–2. Overview of KS57C0404/C0408 Pin Data
Pin Names
P0.0–P0.3
P1.0–P1.2
P1.3
P2.0–P2.3
P3.0–P3.1
P3.2–P3.3
P4.0–P4.3
P5.0–P5.3
P6.0–P6.3
P7.0–P7.3
P8.0–P8.3
Xin, Xout
RESET
TEST
NC
VDD, VSS
Share Pins
SCK, SO, SI, BTCO
INT0, INT1, INT2
INT4
TCLO0, TCLO1, CLO,
BUZ
TCL0, TCL1
–
–
KS0–KS3
KS4–KS7
–
–
–
–
–
–
I/O Type
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
–
I
I
–
–
Reset Value
Input
Input
Input
Input
Input
Input
(NOTE)
Input
Input
–
–
–
–
–
Circuit Type
D-1
A-3
B-4
D
D-1
D
E-2
D-1
D-2
–
B
–
–
–
NOTE: When pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to
high impedance.
1–11
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| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet KS57P0408.PDF ] | |
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