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PDF KS57C01502 Data sheet ( Hoja de datos )
| Número de pieza | KS57C01502 | |
| Descripción | (KS57x0150x) single-chip CMOS microcontroller | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KS57C01502/C01504/P01504
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
The KS57C01502/C01504 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The KS57P01504 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are
the same to KS57C01502/C01504. With a four-channel comparator, eight LED direct drive pins, serial I/O
interface, and its versatile 8-bit timer/counter, the KS57C01502/C01504 offers an excellent design solution for a
wide variety of general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the KS57C01502/C01504's advanced CMOS technology provides for
very low power consumption and a wide operating voltage range — all at a very low cost.
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KS57C01502/C01504/P01504
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions can
always address the PSW regardless of the current value of data memory enable flags.
Before an interrupt or subroutine is processed, the PSW values are pushed onto the stack in data memory bank 0.
When the service routine is completed, the PSW values are restored.
IS1
IS0
EMB
ERB
C SC2 SC1 SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags
(SC0–SC2) using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit registers store address values used to access specific memory and register banks: the select memory
bank register, SMB, and the select register bank register, SRB.
'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory
address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you can
use the instruction 'SRB n'.
The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware.
The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To drive
KS57C01502/C01504 using an external clock source, the external clock signal should be input to Xin, and its
inverted signal to Xout.
4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock
signal (fx) can be divided internally to produce three CPU clock frequencies — fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by
peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0–KS2) detects
falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The
following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
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KS57C01502/C01504/P01504
PRODUCT OVERVIEW
Pin Name
Table 1-1. KS57C01502/C01504 Pin Descriptions (Continued)
Pin
Type
Description
Quasi-interrupt input with falling edge detection
Number
26-28(28-30)
Share Pin
P6.0–P6.2
VDD
VSS
TEST
Xin, Xout
— Main power supply
— Ground
I Reset signal
I Test signal input (must be connected to VSS)
— Crystal or ceramic oscillator signal for system clock
30(32)
1(1)
7(7)
4(4)
3,2(3,2)
—
—
—
—
—
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
Table 1-2. Overview of KS57C01502/C01504 Pin Data
SDIP Pin
Numbers
1
2,3
4
5,6
7
8-10
11-14
15-17
18-21
22-25
26-29
30
Pin
Names
VSS
Xout, Xin
TEST
P1.0, P1.1
P0.0 - P0.2
P2.0 - P2.3
P3.0 - P3.2
P4.0 - P4.3
P5.0 - P5.3
P6.0 - P6.3
VDD
Share
Pins
INT0, INT1
, SO, SI
CIN0 - CIN3
TCL0, TCLO0,
CLO
KS0, KS1, KS2,
BUZ
I/O
Type
I
I
I
I/O
I
I/O
I/O
I/O
I/O
Reset
Value
Input
Input
Input
Input
Input
Input
Input
NOTE: I/O circuit type F-2 is implemented for P2.3 only.
Circuit
Type
A-3
B
D-1
F-1, F-2 (note)
D-1
E
E
D-1
1-11
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| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet KS57C01502.PDF ] | |
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