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Número de pieza | NL6448BC33-54 | |
Descripción | TFT COLOR LCD MODULE | |
Fabricantes | NEC | |
Logotipo | ||
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TFT COLOR LCD MODULE
NL6448BC33-54
26.4cm (10.4 Type)
VGA
DATA SHEET
DOD-PD-0072 (2nd edition)
This DATA SHEET is updated document from
DOD-M-1355(1).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-0072 (2nd edition)
Published date: June 2003 CP(N)
1 NEC LCD Technologies, Ltd.
2003 All rights reserved.
1 page www.DataSheet4U.com
NL6448BC33-54
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
Backlight
Power consumption
211.2 (W) × 158.4 (H) mm (typ.)
26 cm (10.4 inches)
a-Si TFT active matrix
262,144 colors
640 (H) × 480 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.11 (W) × 0.33 (H) mm
0.33 (W) × 0.33 (H) mm
243.0 (W) × 185.1 (H) × 10.5 (D) mm (typ.)
465 g (typ.)
350:1 (typ.)
At the contrast ratio 10:1
• Horizontal: Right side 45° (typ.), Left side 45° (typ.)
• Vertical: Up side 30° (typ.), Down side 20° (typ.)
At DPS= Low or Open: Normal scan
• Viewing direction without image reversal: down side (6 o'clock)
• Viewing direction with contrast peak: normal axis
• Viewing angle with optimum grayscale (γ=2.2): normal axis
Clear
3H (min.) [by JIS K5400]
At LCD panel center
40 % (typ.) [against NTSC color space]
Ton (white 90%→ black 10%)
15 ms (typ.)
At IBL= 5.0mArms / lamp
220 cd/m2 (typ.)
6-bit digital signals for data of RGB colors,
Dot clock (CLK), Data enable (DE),
Horizontal synchronous signal (Hsync),
Vertical synchronous signal (Vsync)
LCD panel signal processing board: 3.3V or 5.0V
Edge light type: 2 cold cathode fluorescent lamps
Replaceable part
• Lamp holder set: Type No. 104LHS35
Recommended inverter (Option)
• Inverter: Type No.: 104PW161, 104PW191
At IBL= 5.0mArms / lamp and checkered flag pattern
5.8 W (typ.)
DATA SHEET DOD-PD-0072 (2nd edition)
5
5 Page www.DataSheet4U.com
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 Sequence for LCD panel signal processing board
VCC
Note1
3.0V or 4.75V
0V
Display and
function signals
Note2
ON
Tr < 30ms
0ms < t < 35ms
VALID period
NL6448BC33-54
OFF
Toff > 50ms
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V in
"VCC = 3.3V" or 4.75V in "VCC = 5.0V", a protection circuit may work, and then this
product may not work.
Note2: Display (CLK, Hsync, Vsync, DE, R0 to R5, G0 to G5, B0 to B5) and function (DPS)
signal must be Low or High-impedance, exclude the VALID period (See above sequence
diagram), in order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is
working, even if the signal input to it once again, it might not work normally. If customer
stops the display and function signals, they should be cut VCC.
4.4.2 Sequence for backlight inverter (Option)
Display and
function signals
Note1
Note2
VALID period
VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of
display and function signals, in order to avoid unstable data display.
DATA SHEET DOD-PD-0072 (2nd edition)
11
11 Page |
Páginas | Total 28 Páginas | |
PDF Descargar | [ Datasheet NL6448BC33-54.PDF ] |
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