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PDF IDTAMB0480 Data sheet ( Hoja de datos )
| Número de pieza | IDTAMB0480 | |
| Descripción | ADVANCED MEMORY BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER
FOR FULLY BUFFERED DIMM
MODULES
IDTAMB0480
PRODUCT
BRIEF
FEATURES:
• Advanced Memory Buffer for Fully buffered DIMMs
• 3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)
• Support for up to eight DIMMs per channel
• Repeater Mode for extending FB-DIMM links
• Northbound and Southbound single lane fail over and channel
error detection
• Voltage and Timing margin high-speed I/O test capability
• Fully Supports the FB-DIMM configuration register set
• Test features supported include:
- Integrated thermal sensor and status indicator
- Supports MEMBIST, IBIST and Virtual Host mode
- Transparent mode and direct access mode for DRAM testing
• Complies with JEDEC Architecture and Protocol Specification
• Available in 655 ball FCBGA package
EXPANDED FEATURES:
• Wide range DDR Timing Control
• Superfine adjustment for DDR timing
• Wide range of DDR slew rate control
• Slew rate controllable independent of output impedance
• High speed SMBus in test mode
• IBIST IDT PRBS Generator
DESCRIPTION:
The fully buffered dual in-line memory module (FB-DIMM) is the next
generation memory architecture to meet the growing memory requirement of
servers and workstations. The IDT Advanced Memory Buffer (AMB) chip is the
essential building block located on each FB-DIMM. The IDT AMB receives
commands and data from the host controller to control and write/read data to/
from the DRAMs on the DIMM. Commands and write data are sent southbound
from the host controller to AMBs in a daisy chain fashion and interpreted by the
target AMB. Status and read data are sent northbound from AMBs to the host
controller also in a daisy chain fashion, passing through non-target AMBs. This
unique channel structure alleviates buffer loading issues common in registered
DIMM technology, enabling designers to use a large number of DIMMs within
a single system.
IDTAMB0480complieswiththelatest JEDECdefinedFB-DIMMArchitecture
and Protocol Specification and supports DDR2-533 and DDR2-667 DRAM.
It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480
supportsservers,workstations,storagedevicesandcommunicationapplications
that support the next generation FB-DIMM architecture.
FDB MEMORY CHANNEL
Host
Memory
Controller
14
10
DDR2
DDR2
DDR2
DDR2
IDT
AMB
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
IDT
AMB
DDR2
DDR2
DDR2
DDR2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
c 2006 Integrated Device Technology, Inc.
1
DDR2
DDR2
DDR2
DDR2
IDT
AMB
DDR2
DDR2
DDR2
DDR2
Up to 8 modules
DDR2
DDR2
DDR2
DDR2
IDT
AMB
DDR2
DDR2
DDR2
DDR2
APRIL 2006
DSC - 7042/2
1 page  
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
655 BALL BGA PACKAGE ATTRIBUTES
COMMERCIAL TEMPERATURE RANGE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
5
5 Page 
IDTAMB0480
ADVANCEDMEMORYBUFFERFORFULLYBUFFEREDDIMM
PIN DESCRIPTION (CONT.)
COMMERCIAL TEMPERATURE RANGE
Signal
Clocking
SCK
SCK
Type
I
I
PLLTSTO
O
VCCA PLL
A
VSSA PLL
A
System Management
SCL I/O
SDA I/O
SA[2:0]
Reset
RESET
Miscellaneous Test
TEST (4 pins) N C
TESTLO (5 pins) A
TESTLO_AB20 A
TESTLO_AC20 A
Power Supplies
VCC (24 pins)
A
VCCFBD (8 pins) A
VDD (24 pins)
A
VSS (156 pins)
A
VDDSPD
A
Other Pins
BFUNC
I
RFU (18 pins) N C
Other No Connect Pins
NC (129 pins) N C
Description
AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop in the AMB core. Phase Locked Loops in
the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
AMB Clock Complement: This is the other differential reference clock input to the Phase Locked Loop in the AMB core. Phase LockedLoops
in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
PLL Clock Observability Output: This pin can be used to observe VCO, reference clock, core clock, etc. For system debug and design
characterization.
VCC: PLL Analog Voltage for the core PLL
VSS: PLL Analog Voltage for the core PLL
SMBus Clock
SMBus Address/Data
DIMM Select ID
Power Good Reset
Pin for debug and test. Must be floated on DIMM.
Pin for debug and test. Must be tied to Ground on DIMM
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.
1.5V nominal supply for core I/O
1.5V nominal supply for FBD high speed I/O
1.8V nominal supply for DDR I/O
Ground
3.3V nominal supply for SMB receivers and ESD diodes
Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FBDIMM. When BFUNC = 1, AMB is used as either a repeater
or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground
Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in future AMB
implementations.
No Connect pins
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet IDTAMB0480.PDF ] | |
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