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PDF IDT70P3337 Data sheet ( Hoja de datos )

Número de pieza IDT70P3337
Descripción (IDT70P3307 / IDT70P3337) 1024K/512K x18 SYNCHRONOUS DUAL QDR-II
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1024K/512K x18
SYNCHRONOUS
DUAL QDR-IITM
PRELIMINARY DATASHEET
IDT70P3307
IDT70P3337
®
Features
18Mb Density (1024K x 18)
– Also available 9Mb Density (512K x 18)
QDR-II x 18 Burst-of-2 Interface
– Commercial: 233MHz, 250MHz
Separate, Independent Read and Write Data Ports
– Supports concurrent transactions
Dual Echo Clock Output
Two-Word Burst on all DPRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
– One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
– Four word burst data (Two Read and Two Write) per clock on
each port
– Four word transfers per clock cycle per port (four word bursts
on 2 ports)
Port Enable pins (E0,E1) for depth expansion
Dual Echo Clock Output with DLL-based phase alignment
High Speed Transceiver Logic inputs that can be scaled to
receive signals from 1.4V to 1.9V
Scalable output drivers
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V
– Output impedance adjustable from 35 ohms to 70 ohms
1.8V Core Voltage (VDD)
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)
JTAG Interface - IEEE 1149.1 Compliant
Functional Block Diagram
EL[1:0]
D0 L - D1 7 L
KL
KL
A0L- A18L(2)
RL
WL
BW0 L - BW1 L
KL
KL
VREFL
LEFT PORT
DATA
REGISTER
AND LOGIC
ZQL (1)
Q0 L - Q1 7 L
CQL, CQL
LEFT PORT
ADDRESS
REGISTER
AND LOGIC
VREFL
KL
KL
CL
CL, CL
OR KL, KL
TDI
TDO
EP[1:0]
WRITE DRIVER
1024/512K x 18
MEMORY
ARRAY
ADDRESS DECODE
JTAG
TCK
TMS
TRST
VREFR
KR
KR
CR
CR, CR
OR KR, KR
RIGHT PORT
DATA
REGISTER
AND LOGIC
ZQR (1)
Q0 R - Q1 7 R
CQR, CQR
RIGHT PORT
ADDRESS
REGISTER
AND LOGIC
ER[1:0]
D0 R - D1 7 R
KR
KR
A0R- A18R(2)
RR
WR
BW0 R - BW1 R
KR
KR
VREFR
6725 drw01
NOTES:
1. Input pin to adjust the device outputs to the system data bus impedance.
2. Address A18 is a INC for IDT70P3337. Disabled input pin (Diode tied to VDD and VSS).
July 16, 2007
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."
DSC-6725/1

1 page




IDT70P3337 pdf
18/9Mb QDR-IITM x18 IDT70P3307/70P3337
SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet
Commercial Temperatue Range
Pin Definitions
andSymbol(-
1)
Pin Function
Description
D[17:0]X
BW0X, BW1X
A[18:0]X(2)
Q[17:0]X
WX
RX
CX
CX
KX
KX
Input Data input signals, sampled on the rising edge of K and K clocks during valid write operations
Synchronous
Input
Synchronous
Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is
written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the
data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW0 controls D[8:0], BW1 controls D[17:9].
Input Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K
Synchronous clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs
are ignored when the appropriate port is deselected.
Output
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during
Synchronous Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[17:0] are automatically tri-stated.
Input Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will
Synchronous deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored.
Input Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the
Synchronous Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next
rising edge of the C clock. (DOFFX = 1). Each read access consists of a burst of two sequential transfers.
Input Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further details.
Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times
of various devices on the board back to the controller. See application example for further details.
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[17:0] when in single clock mode.
All accesses are initiated on the rising edge of K.
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device. Drives out data through Q[17:0] when in single clock mode.
CQX
CQX
ZQX
EP[1:0]
EX[1:0]
DOFFX
MRST
DEPTH
TDO
TCK
TDI
TMS
TRST
INC
VREFX
VDD
VSS
VDDQX
Output Clock Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop when the output data is tri-stated.
Output Clock
Synchronous Echo Clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop wehen the output data is tri-stated.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
Input
EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use
Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.
Input
Syncronous
Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3307 devices. If a customer
does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop
using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of K for write operations.
Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.
There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured.
Input Master Reset pin. When held low will reset the device.
Asynchronous
Input
The DEPTH pin selects between the 18Mb and the 9Mb density, and it needs to be tied to V DD or Vss. DEPTH = Vss puts the device in the 18Mb configuration, and
DEPTH = VDD puts the device in a 9Mb configuration.
Output
TDO pin for JTAG.
Input TCK pin for JTAG.
Input TDI pin for JTAG.
Input TMS pin for JTAG.
Input Reset pin for JTAG.
Asynchronous
Should be tied to VCC or VSS only, or can be left as a floating pin.
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground Ground for the device. Should be connected to ground of the system.
Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6725 tbl01
NOTES:
1. "X" = "L" for the Left Port pins and "X" = "R" for the Right Port pins.
2. A[17:0]x for IDT70P3337.
5 July 16, 2007

5 Page





IDT70P3337 arduino
18/9Mb QDR-IITM x18 IDT70P3307/70P3337
SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet
Commercial Temperatue Range
AC Electrical Characteristics
(VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA(8) = 0 to 70°C)
Commercial
Com'l & Ind'l
250MHz
233MHz
Symbol
Clock Parameters
Parameter
Min. Max. Min. Max. Unit Notes
tKHKH Average clock cycle time (K,K,C,C)
4.00 6.30 4.30 7.20 ns
tKC var Clock Phase Jitter (K,K,C,C)
__ 0.20 __ 0.20 ns 1,5
tKHKL Clock High Time (K,K,C,C)
1.60 __ 1.80 __ ns 9
tKLKH Clock LOW Time (K,K,C,C)
1.60 __ 1.80 __ ns 9
tKHKH Clock to clock (KK,CC)
1.80 __ 2.00 __ ns 10
tKHKH Clock to clock (KK,CC)
1.80 __ 2.00 __ ns 10
tKHCH Clock to data clock (KC,KC)
0.00 1.80 0.00 2.00 ns
tKC lock DLL lock time (K, C)
1024 __ 1024 __ cycles 2
tKC reset K static to DLL reset
30 __ 30 __ ns
Output Parameters
tCHQV C,C HIGH to output valid
__ 0.45 __ 0.45 ns 3
tCHQX C,C HIGH to output hold
-0.45 __ -0.45 __ ns 3
tCHCQV C,C HIGH to echo clock valid
__ 0.45 __ 0.45 ns 3
tCHCQX C,C HIGH to echo clock hold
-0.45 __ -0.45 __ ns 3
tCQHQV CQ,CQ HIGH to output valid
__ 0.30 __ 0.32 ns
tCQHQX CQ,CQ HIGH to output hold
-0.30 __ -0.32 __ ns
tCHQZ C HIGH to output High-Z
__ 0.45 __ 0.45 ns 3,4,5
tCHQX1 C HIGH to output Low-Z
-0.45 __ -0.45 __ ns 3,4,5
Set-Up Times
tAVKH Address valid to K,K rising edge
0.35 __ 0.37 __ ns 6
tIVKH Control inputs valid to K,K rising edge
0.35 __ 0.37 __ ns 7
tDVKH Date-in valid to K, K rising edge
0.35 __ 0.37 __ ns
Hold Times
tKHAX K,K rising edge to address hold
0.35 __ 0.37 __ ns 6
tKHIX K,K rising edge to control inputs hold
0.35 __ 0.37 __ ns 7
tKHDX K,K rising edge to data-in hold
0.35 __ 0.37 __ ns
Port-to-Port Delay
tCO Clock-to-Clock Offset
4.00 4.30 ns
NOTES:
6725 tbl15
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No. 65
(EIA/JESD65) page.
2. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD, VDDQ and input clock are stable.
3. If C, C are tied High, K, K become the references for C, C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at 0°C and 1.9V tCHQZ, is a MAX parameter
that is worst case at 70°C and 1.7V.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W, BW0, BW1, E0, E1.
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60%of the cycle time (tKHKH).
10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
11
July 16, 2007

11 Page







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