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PDF IDT70P247L Data sheet ( Hoja de datos )
| Número de pieza | IDT70P247L | |
| Descripción | (IDT70P247L / IDT70P257) VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70P257/247L
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Industrial: 55ns (max.)
◆ Low-power operation
IDT70P257/247L
Active: 27mW (typ.)
Standby: 3.6µW (typ.)
◆ Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆ IDT70P257/247 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
◆ M/S = VDD for BUSY output flag on Master
M/S = VSS for BUSY input on Slave
◆ Input Read Register
◆ Output Drive Register
◆ BUSY and Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ LVTTL-compatible, single 1.8V (±100mV) power supply
◆ Available in 100 Ball 0.5mm-pitch BGA
◆ Industrial temperature range (-40°C to +85°C)
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL(2,3)
A12L(1)
A0L
I/O
Control
I/O
Control
Address
Decoder
MEMORY
ARRAY
Address
Decoder
CEL
OEL
R/WL
IRR0,IRR1
CEL
OEL
R/WL
13
SEML
INTL(3)
NOTES:
1. A12X is a NC for IDT70P247.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2004 Integrated Device Technology, Inc.
INPUT
READ REGISTER
AND
OUTPUT
DRIVE REGISTER
SFEN
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
1
CER
OER
R/WR
OD R0 - ODR4
13
CER
OER
R/WR
,
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR(2,3)
A12R(1)
A0R
SEMR
INTR(3)
5684 drw 01
FEBRUARY 2004
DSC-5684/1
1 page  
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT Output Capacitance
VOUT = 3dV
11 pF
NOTES:
5684 tbl 07
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Preliminary
Industrial Temperature Range
Maximum Operating Temperature
and Supply Voltage(1)
Grade
Ambient
Temperature
GND
VDD
Industrial
-40OC to +85OC
0V 1.8V + 100mV
NOTES:
5684 tbl 05
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating Conditions
Symbol Parameter
Min.
Typ.
Max.
Unit
VDD Supply Voltage(3)
1.7 1.8
1.9 V
VSS Ground
00
0V
VIH Input High Voltage
1.2
___
VDD + 0.2
V
VIL Input Low Voltage
-0.2
___
0.4 V
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
3. M/S operates at the VDD and VSS voltage levels.
5684 tbl 06
6.542
5 Page 
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Preliminary
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
ADDRESS
OE
(9)
CE or SEM
tWC
tAW
tHZ (7)
CE or SEM(9)
R/W
DATAOUT
DATAIN
tAS (6)
(4)
tWP (2)
tWZ (7)
tDW
tWR(3)
tOW
tDH
(4)
,
5684 drw 06
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
ADDRESS
CE or SEM (9)
tWC
tAW
UB or LB(9)
tAS(6)
tEW (2)
tWR(3)
R/W
tDW tDH
DATAIN
,,
5684 drw 07
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
61.412
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet IDT70P247L.PDF ] | |
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