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PDF ICS889872 Data sheet ( Hoja de datos )
| Número de pieza | ICS889872 | |
| Descripción | DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION | |
| Fabricantes | IDT | |
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PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889872
General Description
The ICS889872 is a high speed Differential-to-
ICS LVDS Buffer/Divider w/Internal Termination and is a
HiPerClockS™ member of the HiPerClockS™family of high
performance clock solutions from IDT. The
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
• Three LVDS outputs
• Frequency divide select options: ÷4, ÷6: >2GHz,
÷8, ÷16: >1.6GHz
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: >2GHz
• Cycle-to-cycle jitter: 1ps (typical)
• Total jitter: 10ps (typical)
• Output skew: 7ps (typical), QA/nQA outputs
• Part-to-part skew: 250ps (typical)
• Propagation Delay: 750ps (typical), QA/nQA outputs
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
nRESET/
nDISABLE
Enable
FF
Enable
MUX
IN
50Ω
VT
50Ω
nIN
VREF_AC
S1
S0
Decoder
÷2, ÷4,
÷8, ÷16
QA
nQA
QB0
nQB0
QB1
nQB1
16 15 14 13
QB0 1
12 IN
nQB0 2
11 VT
QB1 3
10 VREF_AC
nQB1 4
9 nIN
5 6 78
ICS889872
16-Lead VFQFN
3mm x 3mm x 0.95mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
1
ICS889872AK REV. A AUGUST 22, 2007
1 page  
ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 4C. Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
RIN
VIH
VIL
VIN
VDIFF_IN
IIN
VREF_AC
Differential Input Resistance (IN, nIN)
Input High Voltage
(IN, nIN)
Input Low Voltage
(IN, nIN)
Input Voltage Swing
Differential Input Voltage Swing
Input Current
(IN, nIN)
Bias Voltage
1.2
0
0.15
0.3
Typical
100
VDD – 1.35
Maximum
VDD
VDD – 0.15
2.8
45
Units
Ω
V
V
V
V
mA
V
Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOUT
VOH
VOL
VCCM
∆VOCM
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
0.925
Typical
350
1.475
1.35
Maximum
50
Units
mV
V
V
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fMAX
Output Frequency
Input Frequency
÷2, ÷4
÷8, ÷16
tPD
Propagation Delay;
NOTE 1, 2
IN-to-Q
Input Swing: <400mV
Input Swing: ≥400mV
tsk(o)
Output Skew;
NOTE 2, 3, 4
QB0-to-QB1
QA-to-QB
tsk(pp)
Part-to-Part Skew; NOTE 2, 4, 5
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2, 6
tjit(j) Total Jitter; NOTE 2
tRR
tR / tF
Reset Recovery Time; NOTE 2
Output Rise/Fall Time; NOTE 2
Minimum
600
Typical
>2
>1.6
750
750
7
60
250
1
10
150
Maximum
Units
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Specs are design targets.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
5
ICS889872AK REV. A AUGUST 22, 2007
5 Page 
ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS889872.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
• Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 80mA = 210mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.210W * 51.5°C/W = 95.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
11
ICS889872AK REV. A AUGUST 22, 2007
11 Page | ||
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| PDF Descargar | [ Datasheet ICS889872.PDF ] | |
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