|
|
PDF ICS889831 Data sheet ( Hoja de datos )
| Número de pieza | ICS889831 | |
| Descripción | 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICS | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS889831 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS889831 is a high speed 1-to-4 Differential-
to-LVPECL/ECL Fanout Buffer and is a member
HiPerClockS™ of the HiPerClockS™family of high performance
clock solutions from ICS. The ICS889831 is
optimized for high speed and very low output
skew, making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre
Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as
LVDS, LVHSTL and CML to be easily interfaced to the input
with minimal use of external components.The device also has
an output enable pin which may be useful for system test
and debug purposes. The ICS889831 is packaged in a small
3mm x 3mm 16-pin VFQFN package which makes it ideal
for use in space-constrained applications.
FEATURES
• 4 differential LVPECL/ECL outputs
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
•
50Ω
internal
input
termination
to
V
T
• Maximum output frequency: > 2.1GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 185ps (maximum)
• Additive phase jitter, RMS: 0.27ps (typical)
• Propagation delay: 570ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.5V ± 5%, 3.3V ± 5%, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.3V ± 5%, 2.5V ± 5%
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
EN
IN 50Ω
VT
nIN
50Ω
D
Q
LE
V
REF_AC
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
1 0 VREF_AC
nQ2 4
9 nIN
5678
Q2
nQ2 ICS889831
16-Lead VFQFN
Q3 3mm x 3mm x 0.95 package body
nQ3 K Package
Top View
889831AK
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 16, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol Parameter
Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VOUT
Output Voltage Swing
VDIFF_OUT Differential Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
VCC - 1.125
VCC - 1.895
0.6
1.2
Typical
VCC - 1.005
VCC - 1.78
Maximum
VCC - 0.935
VCC - 1.67
1.0
2.0
Units
V
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.3V ± 5%, -2.5V ± 5% OR VCC = 2.5 ± 5%, 3.3V ± 5%; VEE = 0V
Symbol Parameter
Condition
Minimum Typical Maximum
fMAX Maximum Output Frequency
tPD
Propagation Delay; (Differential);
NOTE 1
Output Swing ≥ 450mV
Input Swing: 100mV
Input Swing: 800mV
2.1
300
255
435
370
570
485
tsk(o) Output Skew; NOTE 2, 4
30
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
155.52MHz, Integration
Range: 12kHz - 20MHz
0.27
185
tR/tF Output Rise/Fall Time
20% to 80%
100
tS Clock Enable Setup Time EN to IN, nIN
300
tH Clock Enable Hold Time EN to IN, nIN
300
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
250
Units
GHz
ps
ps
ps
ps
ps
ps
ps
ps
889831AK
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 16, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
3.3V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATION INTERFACES
The IN /nIN with built-in 50Ω terminations accepts LVDS, by the most common driver types. The input interfaces sug-
LVPECL, LVHSTL, CML, SSTL and other differential signals. gested here are examples only. If the driver is from another ven-
Both VOUT and VOH must meet the VPP and VCMR input require-
ments. Figures 5A to 5E show interface examples for the
HiPerClockS IN/nIN input with built-in 50Ω terminations driven
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
nation requirements.
3. 3V
3. 3V
LVDS
Zo = 50 Ohm
Zo = 50 Ohm
IN
VT
nIN Receiver
With
Built-In
50 Ohm
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
3. 3V
3. 3V
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
IN
VT
nIN
R1
50
R e c e ive r
With
Built-In
50 Ohm
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
3. 3V
3. 3V
Zo = 50 Ohm
Zo = 50 Ohm
CML- Open Collector
IN
VT
nIN Receiver
With
Built-In
50 Ohm
FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH OPEN COLLECTOR
3. 3V
3. 3V
Zo = 50 Ohm
Zo = 50 Ohm
CML- Built-in 50 Ohm Pull-Up
IN
VT
nIN Receiver
With
Built-In
50 Ohm
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
3. 3V
3.3V
R1 25 Zo = 50 Ohm
Zo = 50 Ohm
SSTL R2 25
IN
VT
nIN Receiver
With
Built-In
50 Ohm
FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
889831AK
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 16, 2005
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS889831.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS889831 | 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER | ICS |
| ICS889832 | 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER |  IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |