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PDF ICS844011I Data sheet ( Hoja de datos )
| Número de pieza | ICS844011I | |
| Descripción | CRYSTAL-TO- LVDS CLOCK GENERATOR | |
| Fabricantes | ICS | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844011I
FEMTOCLOCKS™CRYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS844011I is a Fibre Channel Clock
ICS Generator and a member of the HiPerClocksTM
HiPerClockS™ family of high performance devices from ICS.
The ICS844011I uses an 18pF parallel resonant
crystal over the range of 20.4MHz - 28.3MHz. For
Fibre Channel applications, a 26.5625MHz crystal is used.
The ICS844011I has excellent <1ps phase jitter per-
formance, over the 637kHz - 10MHz integration range. The
ICS844011I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
FEATURES
• (1) Differential LVDS output
• Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
• Output frequency range: 81.66MHz - 113.33MHz
• VCO range: 490MHz - 680MHz
• RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
COMMON CONFIGURATION TABLE - FIBRE CHANNEL
Inputs
Crystal Frequency (MHz) M
26.5625
25
24
24
N
Multiplication
Value M/N
64
64
Output Frequency
(MHz)
106.25
100
BLOCK DIAGRAM
OE Pullup
XTAL_IN
XTAL_OUT
OSC
Phase
Detector
VCO
490MHz - 680MHz
N = ÷6 (fixed)
M = ÷24 (fixed)
Q
nQ
PIN ASSIGNMENT
VDDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8 VDD
7Q
6 nQ
5 OE
ICS844011I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844011AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 28, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844011I
FEMTOCLOCKS™CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
POWER SUPPLY
+ Float GND -
LVDS
Qx SCOPE
nQx
2.5V±5%
POWER SUPPLY
+ Float GND -
LVDS
Qx SCOPE
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Phase Noise Mask
f1 Offset Frequency f2
RMS Jitter = Area Under the Masked Phase Noise Plot
nQ
Q
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
RMS PHASE JITTER
Clock
20%
Outputs
80%
tR
80%
tF
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VVDDDD
out
VSW I N G
20%
DC Input LVDS
out
➤
VOS/Δ VOS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VVDDDD
DC Input LVDS
out
➤
100 VOD/Δ VOD
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844011AGI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 28, 2005
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ICS844011I.PDF ] | |
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