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PDF ICS844003I Data sheet ( Hoja de datos )
| Número de pieza | ICS844003I | |
| Descripción | CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844003I is a 3 differential output LVDS
ICS Synthesizer designed to generate Ethernet refer-
HiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of 4 fre-
quency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I
has 2 output banks, Bank A with 1 differential LVDS output
pair and Bank B with 2 differential LVDS output pairs.
The two banks have their own dedicated frequency se-
lect pins and can be independently set for the frequen-
cies mentioned above. The ICS844003I uses ICS’ 3rd gen-
eration low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS844003I is packaged
in a small 24-pin TSSOP package.
BLOCK DIAGRAM
CLK_ENA Pullup
DIV_SELA[1:0]
VCO_SEL Pullup
TEST_CLK Pulldown
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL Pullup
1
FB_DIV Pulldown
DIV_SELB[1:0]
MR Pulldown
CLK_ENB Pullup
Phase
Detector
VCO
560-700MHz
FB_DIV
0 = ÷20 (default)
1 = ÷24
FEATURES
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
• Using a 31.25MHz or 26.041666MHz crystal, the two
output banks can be independently set for 625MHz,
312.5MHz, 156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.63ps (typical)
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
0 0 ÷1
0 1 ÷2 (default)
0 1 0 ÷4
1 1 ÷5
1
PIN ASSIGNMENT
DIV_SELB0
VCO_SEL
MR
1
2
3
24 DIV_SELB1
2 3 VDDO_B
22 QB0
VDDO_A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0
4
5
6
7
8
9
10
11
12
21 nQB0
20 QB1
19 nQB1
18 XTAL_SEL
17 TEST_CLK
16 XTAL_IN
15 XTAL_OUT
14 GND
13 DIV_SELA1
ICS844003I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
QA0
nQA0
0 0 ÷1
0 1 ÷2
1 0 ÷4 (default)
1 1 ÷5
QB0
nQB0
QB1
nQB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI
www.icst.com/products/hiperclocks.html
REV. B AUGUST 25, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
Inputs, VI
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VDD
V
DDA
VDDO_A, B
IDD
IDDA
IDDO_A, B
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.135
3.135
3.3
3.3
3.3
99
10
52
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
TABLE
4B.
LVCMOS
/
LVTTL
DC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO_A
=
V
DDO_B
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VIH Input High Voltage
VDD = 3.3V
VDD = 2.5V
VIL Input Low Voltage
VDD = 3.3V
VDD = 2.5V
TEST_CLK, MR, FB_DIV
VDD = VIN = 3.465V
IIH
Input
DIV_SELA1, DIV_SELB0
High Current DIV_SELB1, DIV_SELA0,
or 2.625V
V = V = 3.465V
VCO_SEL, XTAL_SEL,
DD IN
CLK_ENA, CLK_ENB
or 2.625V
2
1.7
-0.3
-0.3
VDD + 0.3
VDD + 0.3
0.8
0.7
150
5
IIL
Input
Low Current
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
VDD = 3.465V or 2.625V,
VIN = 0V
VDD = 3.465V or 2.625V,
-5
-150
CLK_ENA, CLK_ENB
V = 0V
IN
Units
V
V
V
V
µA
µA
µA
µA
844003AGI
www.icst.com/products/hiperclocks.html
5
REV. B AUGUST 25, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
70°C/W
1
65°C/W
TRANSISTOR COUNT
The transistor count for ICS844003I is: 3394
2.5
62°C/W
844003AGI
www.icst.com/products/hiperclocks.html
11
REV. B AUGUST 25, 2005
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS844003I.PDF ] | |
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