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PDF 89HPES16T4G2 Data sheet ( Hoja de datos )

Número de pieza 89HPES16T4G2
Descripción 16-Lane 4-Port Gen2 PCI Express Switch
Fabricantes IDT 
Logotipo IDT Logotipo



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16-Lane 4-Port
Gen2 PCI Express® Switch
®
89HPES16T4G2
Data Sheet
Advance Information*
Device Overview
The 89HPES16T4G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
three downstream ports and supports switching between downstream
ports.
Features
High Performance PCI Express Switch
– Sixteen 5 Gbps Gen2 PCI Express lanes
– Four switch ports
• One x4 upstream port
• Three x4 downstream ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixteen 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
– Supports Hot-Swap
Block Diagram
Frame Buffer
4-Port Switch Core / 16 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 4)
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 32
*Notice: The information in this document is subject to change without notice
(Port 6)
September 4, 2007
DSC 6928

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89HPES16T4G2 pdf
IDT 89HPES16T4G2 Data Sheet
Signal
Type
Name/Description
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK
I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT
I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins (Part 2 of 2)
Signal
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[9]
GPIO[10]
Type
Name/Description
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O expander interrupt 0 input.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 1 of 2)
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September 4, 2007

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89HPES16T4G2 arduino
IDT 89HPES16T4G2 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Condition
Min
RefclkFREQ
TC-RISE
TC-FALL
VIH
VIL
VCROSS
Input reference clock frequency range
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Absolute single-ended crossing point
voltage
Differential
Differential
Differential
Differential
Single-ended
100
0.6
0.6
+150
+250
VCROSS-DELTA
Variation of VCROSS over all rising clock
edges
Single-ended
VRB
TSTABLE
TPERIOD-AVG
TPERIOD-ABS
Ring back voltage margin
Time before VRB is allowed
Average clock period accuracy
Absolute period, including spread-spec-
trum and jitter
Differential
Differential
-100
500
-300
9.847
TCC-JITTER
VMAX
VMIN
Duty Cycle
Cycle to cycle jitter
Absolute maximum input voltage
Absolute minimum input voltage
Duty cycle
-0.3
40
Rise/Fall Matching Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
ZC-DC
Clock source output DC impedance
40
Table 9 Input Clock Requirements
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
AC Timing Characteristics
Typical
Max
1251
4
4
-150
+550
+140
+100
2800
10.203
150
+1.15
60
20
60
Unit
MHz
V/ns
V/ns
mV
mV
mV
mV
mV
ps
ppm
ns
ps
V
V
%
%
Ω
Parameter
PCIe Transmit
UI
TTX-EYE
TTX-EYE-MEDIAN-to-
MAX-JITTER
TTX-RISE, TTX-FALL
TTX- IDLE-MIN
Description
Gen 1
Gen 2
Min1 Typ1 Max1 Min1 Typ1 Max1
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maxi-
mum deviation from the median
TX Rise/Fall Time: 20% - 80%
Minimum time in idle
399.88 400 400.12 199.94 200 200.06
0.75 0.75
0.125
0.125
20
0.15
20
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
Units
ps
UI
UI
UI
UI
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