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PDF RD151TS501US Data sheet ( Hoja de datos )

Número de pieza RD151TS501US
Descripción PLL clock generator series
Fabricantes Renesas Technology 
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RD151TS501US
PLL clock generator series
REJ03D0897-0102
Rev.1.02
Apr 25, 2007
Description
RD151TS501US is phase-locked loop clock generator with high-performance. And RD151TS501US is low-jitters and
will enable high density mounting by shrink small-size package (SSOP-8).
Features
Input frequency:
Output frequency:
27.0 to 36.0 MHz
54.0 to 72.0 MHz (1 : 2), 67.5 to 72.0 MHz (1 : 2.5)
27.0 to 36.0 MHz (1 : 1), 33.75 to 36.0 MHz (1 : 1.25) (Selectable)
Key Specifications
Supply voltages: VDD = 2.7 to 3.6 V
Operating temperature = -10 to 75 °C
Cycle to cycle jitter = ±75 ps typ.
Clock output duty cycle = 50±5%
Stabilization time: 2ms max
Power-down mode is supported
Ordering Information
Part Name
Package Type
RD151TS501USE
SSOP-8 pin
Package Code
(Previous Package Code)
PVSP0008KA–A
(TTP-8DBV)
Package
Abbreviation
US
Taping
Abbreviation (Quantity)
E (3,000 pcs / Reel)
Pin Arrangement
VDD 1
8 DIV2
VDD 2
7 IN
VSS 3
6 SEL
OUT 4
(Top view)
5 PDWN
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 1 of 6

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RD151TS501US pdf
RD151TS501US
Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 3.
VDD decoupling is important to reduce Jitter performance.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
VDD
C2 C1
GND GND
GND
OUT
R1
1
2
3
4
8 DIV2
7 IN
6 SEL
5 PDWN
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF recommended)
R1 = Match value to line impedance.
(Please use R1 if nessesarry)
Figure 3 Recommended circuit configuration
Remark for use
Please do not use the pull-up resistance for the OUT terminal to prevent wrong operation of IC.
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
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