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PDF GS1522 Data sheet ( Hoja de datos )

Número de pieza GS1522
Descripción HDTV Serial Digital Serializer
Fabricantes Gennum Corporation 
Logotipo Gennum Corporation Logotipo



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HD-LINX GS1522
HDTV Serial Digital Serializer
FEATURES
• SMPTE 292M compliant
• 20:1 parallel to serial conversion
• NRZ(I) encoder & SMPTE scrambler with selectable
bypass
• NRZ to NRZ(I) serial data conversion
• 1.485Gb/s and 1.485/1.001Gb/s operation
• lock detect output
• selectable DUAL or QUAD 75cable driver outputs
• 8 bit or 10 bit input data support
• 20 bit wide inputs
• Pb-free and Green
• 3.3V and 5V CMOS/TTL compatible inputs
• single +5.0V power supply
APPLICATIONS
SMPTE 292M Serial Digital Interfaces for Video Cameras,
Camcorders, VTRs, Signal Generators, Portable Equip-
ment, and NLEs.
DATA SHEET
DESCRIPTION
The GS1522 is a monolithic bipolar integrated circuit
designed to serialize SMPTE 274M and SMPTE 260M bit
parallel digital signals.
This device performs the following functions:
• Sync word mapping for 8-bit/10-bit operation.
• Parallel to Serial conversion of Luma & Chroma data
• Interleaving of Luma and Chroma data
• Data Scrambling (using the X9+X4+1 algorithm)
• Conversion of NRZ to NRZI serial data (using the (X+1)
algorithm)
• Selectable DUAL or QUAD 75Cable Driver outputs
• Lock Detect Output
• 1.485Gb/s or 1.485/1.001Gb/s operation
This device requires a single 5V supply and typically
consumes less than 1000mW of power while driving two
75cables.
The GS1522 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
ORDERING INFORMATION
PART NUMBER
GS1522-CQR
GS1522-CQRE3
PACKAGE
128 pin MQFP
128 pin MQFP
TEMPERATURE
0°C to 70°C
0°C to 70°C
Pb-FREE AND GREEN
No
Yes
SYNC_DETECT
_DISABLE
20
DATA_IN[19:0]
PCLK_IN
GO1515
INPUT
LATCH
20
PLL
RESET BYPASS
RSET0
SYNC DETECT
SMPTE
SCRAMBLER
INTERLEAVER
RESET
BYPASS
SCLK
PARALLEL
TO SERIAL
CONVERTER
NRZ TO NRZI
PLOAD
MUTE
O/P0
O/P1
SDO0
SDO0
SDO1
SDO1
RSET1
SDO1_EN
PLL_LOCK
Revision Date: June 2004
FUNCTIONAL BLOCK DIAGRAM
Document No. 522 - 26 - 03
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com

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GS1522 pdf
PIN DESCRIPTIONS
NUMBER
SYMBOL
1, 95
VEE3
2
3, 4, 5, 6, 7, 8,
9, 11, 12, 14,
19, 20, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
42, 43,46, 50,
51, 52, 56, 60,
61, 62, 65, 66,
67, 68, 69, 70,
71, 72, 73, 80,
81, 83, 93, 97,
98, 99, 100,
101, 102, 108,
109, 116, 117,
120, 121
10
PCLK_IN
NC
BUF_VEE
13 XDIV20
15 PLL_LOCK
16 BYPASS
17
18, 26, 27, 28,
29, 30, 59
21, 22, 23, 24,
25, 45, 57
31
44
47, 49
48, 54
53, 55
58
RESET
VEE2
VCC2
SDO1_EN
RSET1
SDO1, SDO1
SDO_NC
SDO0, SDO0
RSET0
GENNUM CORPORATION
LEVEL
Power
TTL
TYPE
Input
Input
DESCRIPTION
Negative Supply. Most negative power supply connection, for input
stage.
Parallel Data Clock. 74.25 or 74.25/1.001MHz
No Connect. These pins are not used internally. These pins should
be floating.
Power
TTL
TTL
TTL
TTL
Power
Power
Power
Analog
Analog
Analog
TEST
TEST
Output
Input
Input
Input
Input
Input
Input
Output
Output
Input
Negative Supply/Test Pin. Most negative power supply connection.
For buffer for oscillator/divider for test purposes only. Leave
floating for normal operation.
Test Pin. Test block output. Leave floating for normal operation.
Status Signal Output. Indicates when the GS1522 is phase locked
to the incoming PCLK_IN clock signal. LOGIC HIGH indicates PLL
is in Lock. LOGIC LOW indicates PLL is out of Lock.
Control Signal Input. Used to bypass the scrambling function if
data is already scrambled by GS1501 or if non-SMPTE encoded
data stream such as 8b/10b is to be transmitted. When BYPASS is
LOW, the SMPTE scrambler and NRZ(I) encoder are enabled.
When BYPASS is HIGH, the SMPTE scrambler and NRZ(I) encoder
are bypassed.
Control Signal Input. Used to reset the SMPTE scrambler. For logic
HIGH; Resets the SMPTE scrambler and NRZ(I) encoder. For logic
LOW: normal SMPTE scrambler and NRZ(I) encoder operation.
Negative Supply. Most negative power supply connection. For
Cable Driver outputs and all other digital circuitry excluding input
stage and PLL stage.
Positive Supply. Most positive power supply connection. For Cable
Driver outputs and all other digital circuitry excluding input stage
and PLL stage.
Control Signal Input. Used to enable or disable the second serial
data output stage. This signal must be tied to GND to enable this
stage. Do not connect to a logic LOW.
Control Signal Input. External resistor is used to set the data output
amplitude for SDO1 and SDO1. Use a ±1% resistor.
Serial Data Output Signal. Current mode serial data output #1.
Use 75±1% pull up resistors to VCC2.
No Connect. Not used internally. This pin must be left floating.
Serial Data Output Signal. Current mode serial data output #0. Use
75± 1% pull up resistors to VCC2.
Control Signal Input. External resistor is used to set the data output
amplitude for SDO0 and SDO0. Use a ±1% resistor.
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GS1522 arduino
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage is 500 x ΙP/2. This
produces two frequencies off from the centre by
ƒ = Kƒ x 500 x ΙP/2.
5.4. Phase Lock Loop Frequency Synthesis
The GS1522 requires the HDTV parallel clock (74.25 or
74.25/1.001MHz) to synthesize a serial clock which is 20
times the parallel clock frequency (1.485MHz) using a
phase locked loop (PLL). This serial clock is then used to
strobe the output serial data. Figure 16 illustrates this
operation. The VCO is normally free-running at a frequency
close to the serial data rate. A divide-by-20 circuit converts
the free running serial clock frequency to approximately that
of the parallel clock. Within the phase detector, the divided-
by-20 serial clock is then compared to the reference
parallel clock from the PCLK_IN pin (2). Based on the
leading or lagging alignment of the divided clock to the
input reference clock, the serial data output is synchronized
to the incoming parallel clock.
GS1522 PLL
PCLK_IN
PHASE
DETECTOR
DIVIDE-BY-20
GO1515
VCO
Fig. 16 Phase Lock Loop Frequency Synthesis
5.5. Lock Logic
Logic is used to produce the PLL_LOCK (15) signal which
is based on the LFS signal and phase lock signal. When
there is no data input, the integrator charges and eventually
saturates at either end. By sensing the saturation of the
integrator, it is determined that no data is present. If there is
no data present or phase lock is low, the lock signal is
made LOW. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled when phase lock is
asserted. The direction of the sweep is changed when LFS
saturates at either end.
6. LBCONT
The LBCONT pin (91) is used to adjust the loop bandwidth
by externally changing the internal charge pump current.
For maximum loop bandwidth, connect LBCONT to the
most positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (RPULL-UP). For
low loop bandwidth, leave LBCONT floating. The formula
below shows the change in the loop bandwidth using
RPULL-UP.
LBW
=
LBWNOMINAL
×
(---2---5----k---------+-----R-----P---U----L--L--------U---P----)
(5k+ RPULL UP)
where LBWNOMINAL is the loop bandwidth when LBCONT is
left floating.
7. LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index. The following table summarizes the
relationship between input jitter modulation index and
bandwidth when RCP1 and CCP3 are not used. See the
Typical Application Circuit for the location of RCP1 and CCP3.
TABLE 1: Relationship Between Input Jitter Modulation Index and
Bandwidth
INPUT JITTER
MODULATION
INDEX
BANDWIDTH
BW JITTER FACTOR
(jitter modulation x BW)
0.05 5.657MHz
282.9kHzUI
0.10 2.828MHz
282.9kHzUI
0.20 1.414MHz
282.9kHzUI
0.50 565.7kHz
282.9kHzUI
The product of the input jitter modulation (IJM) and the
bandwidth (BW) is a constant. In this case, it is 282.9kHzUI.
The loop bandwidth automatically reduces with increasing
input jitter, which results in the cleanest signal possible.
Using a series combination of RCP1 and CCP3 in parallel to
an on-chip resistor (see the Typical Application Circuit) can
reduce the loop bandwidth of the GS1522. The parallel
combination of the resistors is directly proportional to the
bandwidth factor. For example, the on-chip 500resistor
yields 282.9kHzUI. If a 50resistor is connected in parallel,
the effective resistance will be (50:500) 45.45. This
resistance yields a bandwidth factor of
[282.9 x (45.45/500)] = 25.72kHzUI
The capacitance CCP3 in series with the RCP1 should be
chosen such that the RC factor is 50µF. For example,
RCP1=50requires CCP3=1µF.
GENNUM CORPORATION
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