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PDF DS28DG02 Data sheet ( Hoja de datos )
| Número de pieza | DS28DG02 | |
| Descripción | 2kb SPI EEPROM | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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DS28DG02
2kb SPI EEPROM with PIO, RTC,
Reset, Battery Monitor, and Watchdog
GENERAL DESCRIPTION
The DS28DG02 combines 2kb (256 x 8) EEPROM
with 12 PIO lines, a real-time clock (RTC) and
calendar with alarm function, a CPU reset monitor, a
battery monitor, and a watchdog. Communication
with the device is accomplished with an industry-
standard SPI™ interface. The user EEPROM is
organized as four blocks of 64 bytes each with
single-byte and up to 16-byte page write capability.
Additional registers provide access to PIOs and to
setup functions. Individual PIO lines can be
configured as inputs or outputs. The power-on state
of PIOs programmed as outputs is stored in
nonvolatile (NV) memory. All PIOs may be
reconfigured by the user through the serial interface.
The RTC/calendar operates in the 12/24-hour format
and automatically corrects for leap years. Battery
monitor threshold and watchdog timeout are user-
programmable through NV registers. The reset
monitor generates a reset to the CPU if the voltage at
the VCC pin falls below the factory-set limit. The reset
output includes a debounce circuit for manual
pushbutton reset.
APPLICATIONS
Asset-Tracking Systems
Broadband Access Network Equipment
Patient-Monitoring Systems
Home Lighting Control Systems
Holter Heart Monitors
Typical Operating Circuit appears on page 32.
Pin Configuration appears on page 33.
FEATURES
2kb (256 x 8) EEPROM Organized in Four
64-Byte Blocks
Single Byte and Up to 16-Byte EEPROM Write
Sequences
EEPROM Write-Protect Control Pin Protects
1, 2, or All 4 Blocks
Endurance 200k Cycles per Page at +25°C;
10ms (max) EEPROM Write Cycle
SPI Serial Interface Supporting Modes (0,0)
and (1,1) at Up to 2MHz Clock Frequency
12 PIO Lines with LED Drive Capability
Each PIO is Configured to Input or Output,
Open-Drain/Push-Pull on Startup by Stored
Value
All PIOs are Reconfigurable After Startup
RTC/Calendar/Alarm with BCD Format and
Leap-Year Compensation
RTC Controlled Through 32.768kHz, 12.5pF
Crystal or External TCXO
CPU Reset Through Fast-Response Precision
VCC Monitor with Hysteresis or Pushbutton
Battery Monitor 2.5V, 2.25V, 2.0V, 1.75V, -5%
Watchdog Timer 1.6s, 0.8s, 0.4s, 0.2s (typ)
Unique Factory-Programmed 64-Bit Device
Registration Number
Operating Range: 2.2V to 5.25V,
-40°C to +85°C
±4kV IEC 1000-4-2 ESD Protection Level
(Except Crystal Pins)
Available in 28-Lead, 4.4mm TSSOP or
36-Lead 6mm × 6mm QFN Package
ORDERING INFORMATION
PART
TEMP RANGE
DS28DG02E-3C+
-40°C to +85°C
DS28DG02E-3C+T
-40°C to +85°C
DS28DG02G-3C+
-40°C to +85°C
DS28DG02G-3C+T
-40°C to +85°C
VCC TRIP
3.3V -5%
3.3V -5%
3.3V -5%
3.3V -5%
PIN-PACKAGE
28 TSSOP-EP* (4.4mm)
28 TSSOP-EP* T&R
36 TQFN-EP* (6mm × 6mm)
36 TQFN-EP* T&R
*EP = Exposed Paddle.
+ Denotes lead-free/RoHS compliant device.
For additional VCC monitor trip points or other device options, contact the factory.
Note: Registers are capitalized for clarity.
PKG CODE
U28E+5
U28E+5
T3666+3
T3666+3
SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 061907
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DS28DG02: 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PIN DESCRIPTION
NAME
X1
X2
PIN
TSSOP28
1
2
TQFN36
33
34
RSTZ 3 36
WDI 4 2
WDOZ
5
3
WPZ
PIO0
PIO4
PIO8
GND
PIO10
PIO6
PIO2
VCC
PIO3
PIO7
PIO11
PIO9
PIO5
PIO1
ALMZ
SO
SI
SCK
CSZ
VBAT
N.C.
GND
6
7
8
9
10, 19
11
12
13
14, 15
16
17
18
20
21
22
23
24
25
26
27
28
—
EP
4
5
6
7
9, 19
10
11
12
13, 15
16
17
18
21
22
23
24
25
26
28
30
31
1, 8, 14,
20, 27,
29, 32, 35
EP
FUNCTION
32.768kHz Crystal Connection 1 or 32.768kHz Input from TCXO
32.768kHz Crystal Connection 2
Open-Drain Output Pin (Active Low) for VCC power-fail reset,
watchdog alarm, and Manual Reset Input. See Multifunction
Control/Setup Register description for more information.
Watchdog Input Pin (Active High). See Multifunction Control/Setup
Register description at address 134h for more information.
Open-Drain Output Pin (Active Low) for (user-choice) watchdog
alarm. See Multifunction Control/Setup Register description for more
information.
Hardware Write-Protect Input Pin (Active Low). See the SPI Interface
description for more information.
PIO Line #0
PIO Line #4
PIO Line #8
Ground Supply
PIO Line #10
PIO Line #6
PIO Line #2
Power Supply Input
PIO Line #3
PIO Line #7
PIO Line #11
PIO Line #9
PIO Line #5
PIO Line #1
Open-Drain Output Pin (Active Low) for RTC, battery monitor, and
(user-choice) watchdog alarms. See the Multifunction Control/Setup
Register description for more information.
SPI Serial Data Output (tristate)
SPI Serial Data Input
SPI Serial Clock Input
Chip Select Input (Active Low)
Backup Battery Supply for RTC and RSTZ support.
No Connection
Exposed Paddle. Solder evenly to the board’s ground plane for proper
operation. See Application Note 3273 for additional information.
OVERVIEW
The DS28DG02 features 2kb of EEPROM, 12 bidirectional PIO channels, an RTC with calendar and alarm
function, a watchdog timer, two voltage monitors with precision trip points, and three alarm/reset outputs. Each
DS28DG02 has its own unique registration number, which serves as identification of the product the device is
embedded in. All these resources are accessed through a serial SPI interface, as shown in the block diagram in
Figure 1. The SPI interface automatically adjusts to SPI modes (0,0) and (1,1). The VCC trip point, which controls
the power-fail reset output (RSTZ pin), is set at the factory. The user can set the battery monitor threshold and the
watchdog time-out through software. The RTC uses the common BCD format for time, calendar and day of the
week. The device can be programmed to generate an RTC alarm every second, minute, hour, or day and once a
week or once a month at a user-defined time. RTC, watchdog, and battery alarm can be individually enabled.
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DS28DG02: 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PIO Read Access
ADDR b7 b6 b5 b4 b3 b2 b1 b0
126h
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
127h
0
0
0
0
IV11 IV10
IV9
IV8
There is only read access to these addresses. Bits 4 to 7 of address 127h always read 0. Read access is functional
for all PIOs, regardless of their direction setting. Reported is the logic state of the pin, which may be different from
what the PIO output value register implies.
BIT DESCRIPTION
IVn: Input Value of PIOn
BIT(S)
—
DEFINITION
Logic state read from PIO0 to PIO11 pins. IV0 applies to PIO0, etc.
Legend:
IVn = PIOn XOR’ed with IMSKn
Figure 4 shows a simplified schematic of a PIO. The flip flops are accessed through the PIO Output State (OVn)
and Read Access (IVn) registers and memory addresses 122h to 125 (DIRn, IMSKn, OTn). They are initialized at
power-up or during Refresh (see the SPI Interface Description) according to the data stored at memory addresses
10Ah to 10Fh. When a PIO is configured as input, the PIO output is tri-stated (high impedance). When a PIO is
configured as output, the PIO input is the same as the output state XORed with the corresponding read inversion
bit. The differences of the PIO behavior in low current and high current mode are explained in the PIO Read/Write
Access section near the end of this document.
Figure 4. PIO Simplified Schematic
OTn
from SPI Interface
DIRn
from SPI Interface
OVn
from SPI Interface
OTn
DQ
CLK
DIRn
DQ
CLK
OVn
DQ
CLK
Vcc
PIOn Pin
CLK
IMSKn
from SPI Interface
IMSKn
DQ
CLK
IVn
DQ
CLK
to SPI Interface
11 of 33
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| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet DS28DG02.PDF ] | |
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