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PDF DS1135L Data sheet ( Hoja de datos )
| Número de pieza | DS1135L | |
| Descripción | 3V 3-in-1 High-Speed Silicon Delay Line | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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FEATURES
§ All-silicon timing circuit
§ Three independent buffered delays
§ Stable and precise over temperature and
voltage
§ Leading and trailing edge precision preserves
the input symmetry
§ Standard 8-pin SO
(150mil), and 8-Pin µSOP (118mil)
§ Vapor phase and IR reflow solderable
§ Available in Tape and Reel
§ Delays specified over both commercial and
industrial temperature ranges
§ 3V operation
§ Recommended replacement for DS1033
DS1135L
3V 3-in-1 High-Speed
Silicon Delay Line
PIN ASSIGNMENT
IN1 1 8 VCC
IN2 2 7 OUT1
IN3 3 6 OUT2
GND
4 5 OUT3
DS1135LZ 8-Pin SO (150mil)
DS1135LU 8-Pin µSOP (118mil)
See Mech. Drawings Section
PIN DESCRIPTION
IN1-IN3
- Input Signals
OUT1-OUT3
- Output Signals
VCC
GND
- +3V Supply
- Ground
DESCRIPTION
The DS1135L series is a low-power, 3V high-speed version of the popular DS1013, DS1033, DS1035
series.
The DS1135L series of delay lines have three independent logic buffered delays in a single package. The
device is Dallas Semiconductor’s fastest 3-in-1 delay line. It is available in a standard 8-pin 118mil
µSOP and 150mil 8-pin Mini-SO.
The device features precise leading and trailing edge accuracy. It has the inherent reliability of an all-
silicon delay line solution.
Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972)
371-4348 for further information on custom delay values.
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TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC ): 3.3V ± 0.1V
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50W Max.
Rise and Fall Time: 3.0ns Max. — Measured between 0.6V and 2.4V.
Pulse Width: 500ns
Pulse Period: 1ms
Output Load Capacitance: 15pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
DS1135-L
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
TIMING DIAGRAM
tRISE
PERIOD
tFALL
80%
20%
IN
OUT
1.5V
1.5V
tWI
tPLH
tOR
1.5V
tPHL
1.5V
tWI
tOF
1.5V
NOTES:
1. All voltages are referenced to ground.
2. Power-up time is the time from the application of power to the time stable delays are being produced
at the output.
5 of 6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DS1135L.PDF ] | |
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