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PDF U632H16 Data sheet ( Hoja de datos )
| Número de pieza | U632H16 | |
| Descripción | PowerStore 2K x 8 nvSRAM | |
| Fabricantes | Simtek | |
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Not Recommended For New Designs
U632H16
PowerStore 2K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 2048 x 8 bits
25 ns Access Times
12 ns Output Enable Access
Times
ICC = 15 mA at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power
Up
Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
Unlimited RECALL cycles from
EEPROM
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package: SOP28 (300 mil)
Description
The U632H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U632H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 μF capacitor. Transfers from
the EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U632H16 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 SOP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCCX
W
HSB
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
August 15, 2006
STK Control #ML0046
Pin Description
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
1 Rev 1.1
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previos Data Valid
tv(A) (9)
Output Data Valid
U632H16
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
25
Unit
Min. Max.
tAVAV
tAVAV
tcW
25
ns
tWLWH
tw(W) 20
ns
tWLEH tsu(W) 20
ns
tAVWL
tAVEL
tsu(A)
0
ns
tAVWH tAVEH tsu(A-WH) 20
ns
tELWH
tsu(E)
20
ns
tELEH
tw(E)
20
ns
tDVWH tDVEH
tsu(D)
12
ns
tWHDX tEHDX
th(D)
0
ns
tWHAX tEHAX
th(A)
0
ns
tWLQZ
tdis(W)
10 ns
tWHQX
ten(W)
5
ns
August 15, 2006
STK Control #ML0046
5
Rev 1.1
5 Page 
U632H16
Device Operation
The U632H16 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below VSWITCH. RECALL operations are
automatically initiated upon power up and may occur
also when VCCX rises above VSWITCH after a low power
condition. RECALL cycles may also be initiated by a
software sequence.
SRAM READ
The U632H16 performs a READ cycle whenever E and
G are LOW and HSB and W are HIGH. The address
specified on pins A0 - A10 determines which of the
2048 data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of tcR. If the READ is initiated by E or
G, the outputs will be valid at ta(E) or at ta(G), whichever
is later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid tsu(D) before the end of a W
controlled WRITE or tsu(D) before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Automatic STORE
During normal operation, the U632H16 will draw cur-
rent from VCCX to charge up a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCCX pin drops below VSWITCH, the part
will automatically disconnect the VCAP pin from VCCX
and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of 100 μF (± 20 %) at 6 V.
Each U632H16 must have its own 100 μF capacitor.
Each U632H16 must have a high quality, high fre-
quency bypass capacitor of 0.1 μF connected between
VCAP and VSS, using leads and traces that are as short
as possible. This capacitor do not replace the normal
expected high frequency bypass capacitor between the
power supply voltage and VSS.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITEs have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
Automatic RECALL
During power up an automatic RECALL takes place. At
a low power condition (power supply voltage <
VSWITCH) an internal RECALL request may be latched.
As soon as power supply voltage exceeds again the
sense voltage of VSWITCH, a requested RECALL cycle
will automatically be initiated and will take tRESTORE to
complete.
If the U632H16 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U632H16 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U632H16 implements nonvolatile operation
while remaining compatible with standard 2K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
August 15, 2006
STK Control #ML0046
11
Rev 1.1
11 Page | ||
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| PDF Descargar | [ Datasheet U632H16.PDF ] | |
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