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PDF AZ100LVEL16VT Data sheet ( Hoja de datos )

Número de pieza AZ100LVEL16VT
Descripción ECL/PECL Oscillator Gain Stage & Buffer
Fabricantes Arizona Microtek 
Logotipo Arizona Microtek Logotipo



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AZ100LVEL16VT ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
High Bandwidth for 1GHz
Similar Operation as
AZ100LVEL16VR except in
Disabled Condition: QHG is High
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 3x3 mm or 2x2 mm
MLP Package
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
MLP 8 (2x2x0.75)
AZ100LVEL16VTNA
P9
<Date Code>
1,2,3
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNA+
P9+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNB
P8
<Date Code>
1,2,4
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNB+
P8+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNC
P2
<Date Code>
1,2,5
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNC+
P2+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTND
P3
<Date Code>
1,2
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTND+
P3+
<Date Code>
1,2
MLP 16 (3x3)
AZ100LVEL16VTL
AZM
16T
<Date Code>
1,2
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead (Pb) AZ100LVEL16VTL+ 16T
1,2
Free <Date Code>
DIE
AZ100LVEL16VTXP N/A
6
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Parts marked TNA for date codes prior to 4WW (prior to 2004).
4 Parts marked TNB for date codes prior to 4WW (prior to 2004).
5 Parts marked TNC for date codes prior to 4WW (prior to 2004).
6 Waffle Pack
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯ outputs.
MLP 16, 3x3 mm Package (VTL) or DIE (VTX)
The AZ100LVEL16VTL and AZ100LVEL16VTX provide a selectable enable input (EN) that allows
continuous oscillator operation. See truth table for the Enable function. If Enable pull-up is desired in the
CMOS/TTL mode, an external 20 kΩ resistor connecting EN to VCC will override the on-chip pull-down resistor.
When disabled, the QHG output is forced high and the Q¯ HG output is forced low. The AZ100LVEL16VTL/VTX also
provides a VBB and 470 Ω internal bias resistors from D to VBB and D¯ to VBB. The VBB pin can support 1.5 mA
sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
The outputs Q and Q¯ each have a selectable on-chip pull-down current source. See truth table below for current
source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com

1 page




AZ100LVEL16VT pdf
AZ100LVEL16VT
AZ100LVEL16VTL
MLP 16
3x3 mm
Q Q NC VCC
16 15 14 13
NC 1
12 CS-SEL
D2
11 QHG
D3
10 QHG
VBB 4
9 EN-SEL
5 678
EN NC VEE VEEP
TOP VIEW
Bottom Center Pad may be left open or tied to VEE
12
10
8
6
4
2
0
0
ADJUSTABLE HIGH GAIN OUTPUT CURRENT
20 40 60 80 100 120 140 160 180 200
VEEP TO VEE RESISTOR VALUE (OHMS)
April 2007 * REV - 9
www.azmicrotek.com
5

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AZ100LVEL16VT arduino
AZ100LVEL16VT
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
2.000±0.050
MLP 8
(2x2mm)
TOP VIEW
0.250±0.050 8
7
0.500 bsc
6
5
0.350±0.050
Pin 1 Identification
R0.100 TYP
1
2 1.200±0.050 1.750
exp. pad
3
Ref.
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.750±0.050
0.000-0.050
1 2 34
0.203±0.025
SIDE VIEW
Note: All dimensions are in mm
April 2007 * REV - 9
www.azmicrotek.com
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