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PDF X96012 Data sheet ( Hoja de datos )
| Número de pieza | X96012 | |
| Descripción | Universal Sensor Conditioner | |
| Fabricantes | Intersil Corporation | |
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®
X96012
Universal Sensor Conditioner with Dual Look Up Table Memory and DACs
Data Sheet
March 10, 2005
FN8216.0
FEATURES
• Two Programmable Current Generators
—±3.2 mA max.
—8-bit (256 Step) Resolution
—Internally Programmable full scale Current
Outputs
—External Resistor Pin to set full scale Current
Outputs
• Integrated 8-bit A/D Converter
• Internal Voltage Reference with Output/Input
• Temperature Compensation
—Internal or External Sensor
—-40°C to +100°C Range
—2.2°C / step resolution
—EEPROM Look-up Tables
• Hot Pluggable
• 2176-bit EEPROM
—17 Pages
—16 Bytes per Page
• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
—2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
• Package
—14-Lead TSSOP
APPLICATIONS
• PIN Diode Bias Control
• RF PA Bias Control
• Temperature Compensated Process Control
• Laser Diode Bias Control
BLOCK DIAGRAM
VRef
VSense
Voltage
Reference
ADC
Temperature
Sensor
Mux
Mux
SDA
SCL
WP
A2, A1, A0
2-Wire
Interface
• Fan Control
• Motor Control
• Sensor Signal Conditioning
• Data Aquisition Applications
• Gain vs. Temperature Control
• High Power Audio
• Open Loop Temperature Compensation
• Close Loop Current, Voltage, Pressure, Temper-
ature, Speed, Position Programmable Voltage
sources, electronic loads, output amplifiers, or
function generator
DESCRIPTION
The X96012 is a highly integrated bias controller which
incorporates two digitally controlled Programmable Cur-
rent Generators, temperature compensation with dedi-
cated look-up tables, and supplementary EEPROM
array. All functions of the device are controlled via a 2-
wire digital serial interface.
Two temperature compensated Programmable Cur-
rent Generators, vary the output current with tempera-
ture according to the contents of the associated
nonvolatile look-up table. The look-up table may be
programmed with arbitrary data by the user, via the 2-
wire serial port, and either an internal or external tem-
perature sensor may be used to control the output cur-
rent response.
The integrated General Purpose EEPROM is included
for product data storage.
Look-up
Table 2
Look-up
Table 1
Control
& Status
General
Purpose
Memory
Mux
Mux
DAC 2
DAC 1
R2
I2
I1
R1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X96012
ELECTRICAL CHARACTERISTICS (CONTINUED) (Conditions are as follows, unless otherwise specified)
All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are
over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. All bits in control reg-
isters are “0”. 255Ω, 0.1%, resistor connected between R1 and Vss, and another between R2 and Vss. 400kHz TTL
input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface in “standby” (see notes 1 and 2 on
page 5). WP, A0, A1, and A2 floating. VRef pin unloaded
Symbol
Parameter
Min Typ Max Unit
Test Conditions / Notes
VRefout
Output Voltage at VRef at 1.205 1.21 1.215
25°C
V -20 µA ≤ I(VRef) ≤ 20 µA
RVref
VRef pin input resistance
20
40 kΩ VRM bit = “1”, 25°C
TCOref
Temperature coefficient
of VRef output voltage
-100
+100 ppm/° See note 4 and 5.
C
VRef Range
Voltage range when VRef
is an input
1
1.3 V See note 3.
TSenseRange Temperature sensor
range
-40
100 °C See note 4.
IR
Current from pin R1 or R2
0
to Vss
3200 µA
VPOR
Power-on reset threshold
voltage
1.5
2.8 V
VccRamp
Vcc Ramp Rate
0.2
50 mV /
µs
VADCOK
ADC enable minimum
voltage
2.6
2.8 V See Figure 11.
Notes: 1.
2.
3.
4.
5.
The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after
a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the
correct Slave Address Byte.
tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%.
These parameters are periodically sampled and not 100% tested.
TCOref = [Max V(VREF) - Min V(VREF)] x 106/(1.21V x 140°C)
5 FN8216.0
March 10, 2005
5 Page 
X96012
PRINCIPLES OF OPERATION
CONTROL AND STATUS REGISTERS
The Control and Status Registers provide the user
with a mechanism for changing and reading the value
of various parameters of the X96012. The X96012
contains seven Control, one Status, and several
Reserved registers, each being one Byte wide (See
Figure 4). The Control registers 0 through 6 are
located at memory addresses 80h through 86h
respectively. The Status register is at memory address
87h, and the Reserved registers at memory address
88h through 8Fh.
All bits in Control register 6 always power-up to the
logic state “0”. All bits in Control registers 0 through 5
power-up to the logic state value kept in their corre-
sponding nonvolatile memory cells. The nonvolatile
bits of a register retain their stored values even when
the X96012 is powered down, then powered back up.
The nonvolatile bits in Control 0 through Control 5 reg-
isters are all preprogrammed to the logic state “0” at
the factory.
Bits indicated as “Reserved” are ignored when read,
and must be written as “0”, if any Write operation is
performed to their registers.
A detailed description of the function of each of the
Control and Status register bits follows:
Control Register 0
This register is accessed by performing a Read or
Write operation to address 80h of memory.
BL1, BL0: BLOCK LOCK PROTECTION BITS (NON-
VOLATILE)
These two bits are used to inhibit any write operation
to certain addresses within the memory array. The
protected region of memory is determined by the val-
ues of the two bits as shown in the table below:
Protected Addresses Partition of array
(Size)
locked
00
None (Default)
None (Default)
0 1 00h to 7Fh (128 bytes)
GPM
1 0 00h to 7Fh and 90h to
CFh (192 bytes)
GPM, LUT1
1 1 00h to 7Fh and 90h to GPM, LUT1, LUT2
10Fh (256 bytes)
If the user attempts to perform a write operation to a
protected region of memory, the operation is aborted
without changing any data in the array.
Notice that if the Write Protect (WP) input pin of the
X96012 is active (LOW), then any write operation to
the memory is inhibited, irrespective of the Block Lock
bit settings.
VRM: VOLTAGE REFERENCE PIN MODE (NON-VOLATILE)
The VRM bit configures the Voltage Reference pin
(VRef) as either an input or an output. When the VRM
bit is set to “0” (default), the voltage at pin VRef is an
output from the X96012’s internal voltage reference.
When the VRM bit is set to “1”, the voltage reference
for the VRef pin is external. See Figure 5.
ADCIN: A/D CONVERTER INPUT SELECT (NON-VOLATILE)
The ADCIN bit selects the input of the on-chip A/D
converter. When the ADCIN bit is set to “0” (default),
the output of the on-chip temperature sensor is the
input to the A/D converter. When the ADCIN bit is set
to “1”, the input to the A/D converter is the voltage at
the VSense pin. See Figure 7.
ADCFILTOFF: ADC FILTERING CONTROL (NON-
VOLATILE)
When this bit is“1”, the status register at 87h is
updated after every conversion of the ADC. When this
bit is “0” (default), the status register is updated after
four consecutive conversions with the same result, on
the 6 MSBs.
NV1234: CONTROL REGISTERS 1, 2, 3, AND 4 VOLA-
TILITY MODE SELECTION BIT (NON-VOLATILE)
When the NV1234 bit is set to “0” (default), bytes writ-
ten to Control registers 1, 2, 3, and 4 are stored in vol-
atile cells, and their content is lost when the X96012 is
powered down. When the NV1234 bit is set to “1”,
bytes written to Control registers 1, 2, 3, and 4 are
stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X96012 is powered
down and powered back up. See “Writing to Control
Registers” on page 24.
I1DS: CURRENT GENERATOR 1 DIRECTION SELECT BIT
(NON-VOLATILE)
The I1DS bit sets the polarity of Current Generator 1,
DAC1. When this bit is set to “0” (default), the Current
Generator 1 of the X96012 is configured as a Current
Source. Current Generator 1 is configured as a Cur-
rent Sink when the I1DS bit is set to “1”. See Figure 8.
11 FN8216.0
March 10, 2005
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet X96012.PDF ] | |
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