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PDF X96011 Data sheet ( Hoja de datos )
| Número de pieza | X96011 | |
| Descripción | Temperature Sensor | |
| Fabricantes | Intersil Corporation | |
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®
X96011
Temperature Sensor with Look Up Table Memory and DAC
Data Sheet
October 25, 2005
FN8215.1
FEATURES
• Single Programmable Current Generator
—±1.6 mA max.
—8-bit (256 Step) Resolution
—Internally Programmable full scale Current
Outputs
• Integrated 8-bit A/D Converter
• Internal Voltage Reference
• Temperature Compensation
—Internal Sensor
—-40°C to +100°C Range
—2.2°C / step resolution
—EEPROM Look-up Table
• Hot Pluggable
• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
• 2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
• Package
—14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• PIN Diode Bias Control
• RF PA Bias Control
• Temperature Compensated Process Control
• Laser Diode Bias Control
• Fan Control
• Motor Control
• Sensor Signal Conditioning
• Data Aquisition Applications
• Gain vs. Temperature Control
• High Power Audio
• Open Loop Temperature Compensation
• Close Loop Current, Voltage, Pressure, Temper-
ature, Speed, Position Programmable Voltage
sources, electronic loads, output amplifiers, or
function generator
DESCRIPTION
The X96011 is a highly integrated bias controller which
incorporates a digitally controlled Programmable Cur-
rent Generator, and temperature compensation using
one look-up table. All functions of the device are con-
trolled via a 2-wire digital serial interface.
The temperature compensated Programmable Current
Generator varies the output current with temperature
according to the contents of the associated nonvolatile
look-up table. The look-up table may be programmed
with arbitrary data by the user, via the 2-wire serial
port, and an internal temperature sensor is used to
control the output current response.
Ordering Information
PART NUMBER
PART
TEMP
MARKING RANGE (°C)
PACKAGE
X96011V14I
X96011V I
-40 to 100 14 Ld TSSOP
X96011V14IZ
(Note)
X96011VI Z
-40 to 100 14 Ld TSSOP
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
A0
A1
A2
Vcc
WP
SCL
SDA
1
2
3
4
5
6
7
14 NC
13 NC
12 NC
11 Vss
10 NC
9 NC
8 IOUT
TSSOP 14L
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X96011
D/A CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions)
Symbol
Parameter
Min Typ Max Unit
Test Conditions / Notes
IFS
OffsetDAC
FSErrorDAC
DNLDAC
Iout full scale current
Iout D/A converter offset error
Iout D/A converter full scale error
Iout D/A converter
Differential Nonlinearity
1.56 1.58
1
-2
-0.5
1.6
1
2
0.5
mA DAC input Byte = FFh,
LSB Source or sink mode, V(Iout) is
Vcc–1.2V in source mode and
LSB 1.2V in sink mode.
LSB See notes 1 and 2.
INLDAC
Iout D/A converter Integral
Nonlinearity with respect to a
straight line through 0 and the full
scale value
-1
1 LSB
VISink
I1 Sink Voltage Compliance
1.2
Vcc V In this range the current at I1
vary < 1%
VISource
I1 Source Voltage Compliance
0
Vcc -
1.2
V In this range the current at I1
vary < 1%
IOVER
IUNDER
trDAC
I1 overshoot on D/A Converter data
byte transition
I1 undershoot on D/A Converter
data byte transition
I1 rise time on D/A Converter data
byte transition; 10% to 90%
5
0 µA DAC input byte changing from
00h to FFh and vice
0
µA
versa, V(I1) is Vcc - 1.2V in
source mode and 1.2V in sink
mode.
30 µs See note 3.
TCOI1I2
Temperature coefficient of output
current Iout
±200
ppm/°C See Figure 5.
[ ]Notes: 1.
LSB is defined as
2
3
x
V(VRef)
255
divided by the resistance between R1 or R2 to Vss.
2. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.
DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNLDAC.
INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
3. These parameters are periodically sampled and not 100% tested.
5 FN8215.1
October 25, 2005
5 Page 
X96011
Figure 4. Control and Status Register Format
Byte
Address
MSB
7 6 54
3
80h
Non-Volatile
1
IDS
NV13 ADCfiltOff
0
Iout
Direction
0: Source
1: Sink
Control
1, 3
Volatility
0: Volatile
1: Non-
volatile
ADC
filtering
0: On
1: Off
81h
Volatile or
Non-Volatile
Direct Access to the LUT
Reserved Reserved
LDA5
LDA4
LDA3
2
0
LDA2
1
0
LDA1
LSB
0
0
Register
Name
Control 0
LDA0
Control 1
83h
Volatile or
Non-Volatile
Direct Access to the DAC
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Control 3
85h
Non-Volatile
0
0 DDAS LDAS 0
Direct
Access
to DAC
0: Disabled
1: Enabled
Direct
Access
to LUT
0: Disabled
1: Enabled
0
IFSO1
IFSO0
Control 5
R Selection
00: Reserved
01: Low Internal
10: Middle Internal
11: High Internal (Default)
86h
Volatile
WEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Write
Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC Output
87h
Volatile
AD7
AD6 AD5 AD4
AD3
AD2
AD1
AD0
Control 6
Status
Registers in byte addresses 82h, 84h, and 88h through 8Fh are reserved.
Registers bits shown as 0 or 1 should always use these values for proper operation.
11 FN8215.1
October 25, 2005
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet X96011.PDF ] | |
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