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PDF AZ100EL16VO Data sheet ( Hoja de datos )
| Número de pieza | AZ100EL16VO | |
| Descripción | ECL/PECL Oscillator Gain Stage and Buffer | |
| Fabricantes | AZM | |
| Logotipo |  |
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AZ10EL16VO
AZ100EL16VO
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage and Buffer with Enable
FEATURES
• Green and RoHS Compliant Available
• 250ps Propagation Delay on Q¯ Output
• High Voltage Gain vs. Standard EL16
• For Oscillator Applications
• Available in 2x2 or 3x3mm MLP Package
• 75kΩ Enable Pull-Down Resistor
• S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek Website
DESCRIPTION
The AZ10/100EL16VO is an oscillator gain stage with a high gain output buffer including an enable. The
QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯ outputs. An enable input (E¯N¯ ) allows
continuous oscillator operation. When E¯N¯ is LOW or floating (NC), input data is passed to both sets of outputs.
When E¯N¯ is HIGH, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to
be passed to the Q/Q¯ outputs. The E¯N¯ input can be driven with an ECL/PECL signal or a CMOS logic signal.
The input impedance of the D/D¯ inputs remain constant for all operating modes since forcing the outputs via the
E¯N¯ pin does not power-down the chip but only disables the high gain QHG/Q¯ HG outputs.
Input protection diodes are included on the D/D¯ inputs for enhanced ESD protection.
The EL16VO also provides a VBB output that supports 1.5mA sink/source current. When used, the VBB pin
should be bypassed to ground or VCC via a 0.01μF capacitor.
Any used output must have an external pull down resistor. For 3.3V operation, an 180Ω resistor to VEE is
recommended if an AC coupled load is present. At 5.0V, a 330Ω resistor is recommended for the AC load case.
Alternately, a 50Ω load terminated to VCC – 2V or the Thevenin equivalent may be driven directly. Unused outputs
may be left floating (NC).
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN/PAD DESCRIPTION
Q
PIN FUNCTION
Q D/D¯ Data Inputs
Q/Q¯ Data Outputs
D QHG QHG/Q¯ HG Data Outputs w/High Gain
VBB Reference Voltage Output
D
QHG E¯N¯
Enable Input
VCC Positive Supply
EN VEE Negative Supply
VBB
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
1 page  
AZ10EL16VO
AZ100EL16VO
10K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 3920
4110 3980
4160 4020
VOL
Output LOW Voltage1,2
3050
3350 3050
3370 3050
Input HIGH Voltage
VIH
D/D¯ 1 3770
4570 3830
4620 3870
E¯N¯ 37701
VCC 38301
VCC 38701
Input LOW Voltage
VIL
D/D¯ 1 2700
3500 2740
3520 2760
E¯N¯ VEE
35001 VEE
35201 VEE
VBB Reference Voltage1
3570
3700 3620
3740 3640
Input HIGH Current
IIH
D/D¯ 60
60
E¯N¯ 150
150
Input LOW Current
IIL D/D¯ 0.5
E¯N¯ 3 -1400
0.5
-1400
0.5
-1400
IEE Power Supply Current
40 40
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
3. Specified with E¯N¯ forced to VEE.
25°C
Typ
Max
4190
3370
4640
VCC
3520
35201
3760
60
150
40
Min
4090
3050
3940
39401
2810
VEE
3690
0.5
-1400
85°C
Typ
Max
4280
3405
4690
VCC
3555
35551
3810
60
150
40
Unit
mV
mV
mV
mV
mV
μA
μA
mA
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
Characteristic
Output HIGH Voltage1
-40°C
Min Typ
-1085
Max
-880
Min
-1025
0°C
Typ
Max
-880
Output LOW Voltage1 -1900
-1555 -1900
-1620
Input HIGH Voltage
D/D¯ -1165
-390 -1165
-390
E¯N¯ -1165
VCC -1165
VCC
Input LOW Voltage
D/D¯ -2250
-1475 -2250
-1475
E¯N¯ VEE
-1475 VEE
-1475
Reference Voltage
-1390
-1250 -1390
-1250
Input HIGH Current
D/D¯ 60
60
E¯N¯ 150
150
IIL
Input LOW Current
0.5
IEE Power Supply Current
0.5
40
40
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
Min
-1025
-1900
-1165
-1165
-2250
VEE
-1390
0.5
25°C
Typ
Max
-880
-1620
-390
VCC
-1475
-1475
-1250
60
150
40
Min
-1025
-1900
-1165
-1165
-2250
VEE
-1390
0.5
85°C
Typ
Max
-880
-1620
-390
VCC
-1475
-1475
-1250
60
150
46
Unit
mV
mV
mV
mV
mV
μA
μA
mA
June 2007 * REV - 23
www.azmicrotek.com
5
5 Page 
AZ10EL16VO
AZ100EL16VO
AZ10EL16VOU
AZ100EL16VOU
Q1
10 VCC
Q2
9 QHG
D 3 TSSOP 10 8 QHG
D4
7 VEE
VBB 5
6 EN
AZ10EL16VOD
AZ100EL16VOD
AZ10EL16VOT
AZ100EL16VOT
Q1
D2
VBB / D 3
EN 4
TSSOP 8
SOIC 8
8 VCC
7 QHG
6 QHG
5 VEE
AZ100EL16VON
MLP 8, 2x2mm
Q1
8 VCC
D2
7 QHG
VBB / D 3
6 QHG
EN 4
TOP VIEW
5 VEE
AZ100EL16VONB
MLP 8, 2x2mm
D1
8Q
VBB / D 2
7 VCC
EN 3
6 QHG
VEE 4
TOP VIEW
5 QHG
MLP 8: Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
AZ10/100EL16VOL
Q Q NC VCC
16 15 14 13
NC 1
12 NC
D2
D3
MLP 16,
3x3 mm
11 QHG
10 QHG
VBB 4
56
EN NC
9 NC
78
VEE 10K
MLP 16 (L) Package and DIE:
10K/100K Selection
Connect pin/pad 10K to VEE to select
10K operation. Float (NC) pin/pad 10K
to select 100K operation. VEE
connection must be less than 1Ω.
Pin 6 of the MLP 16 package may be
connected to pin 7 (VEE) with no effect
on the circuit.
MPL 16: Bottom Center Pad may be left
open or tied to VEE. Pin 7 is the VEE return.
June 2007 * REV - 23
www.azmicrotek.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AZ100EL16VO.PDF ] | |
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