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PDF DS26900 Data sheet ( Hoja de datos )
| Número de pieza | DS26900 | |
| Descripción | JTAG Multiplexer/Switch | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev: 072707
DS26900
JTAG Multiplexer/Switch
General Description
The DS26900 is a JTAG signal multiplexer providing
connectivity between one of three master ports and
up to 18 (36 in cascade configuration) secondary
ports. The device is fully configurable from any one of
the three master ports. The DS26900 can
automatically detect the presence JTAG devices on
the secondary ports.
The DS26900 can be used in multiple configurations
including as a single device, two cascaded devices,
or two redundant devices.
All device control and configuration is accomplished
through standard JTAG operations via the selected
master port.
MicroTCA Chassis
ATCA Chassis
AMC Carrier Cards
JSM Modules
System Level JTAG
Applications
MicroTCA JSM Functional Diagram
MCH1
MASTER3
MCH2
MASTER2
CRAFT
MASTER1
DS26900
JTAG
SWITCH
AMC1
AMC2
AMC3
AMC4
AMCn
AMC18
Features
♦ Efficient Solution for Star Architecture JTAG
♦ Provides Transparent Communications
Between the Arbitrated Master and a Selected
Secondary Port
♦ Single-Package Solution Provides 18
Secondary Ports
♦ Two-Package Cascade Configuration
Provides 36 Secondary Ports
♦ Three Arbitrated Master Ports
♦ Autodetection of Port Presence
♦ Internal Pullup/Down Resistors
♦ Two 32-Bit Scratchpad Registers
♦ Four GPIO Pins for Read/Write Control and
Signaling Applications
♦ Operation Up to 50MHz
♦ Signal Path Modification Options
♦ Redundancy with High-Impedance Pin
♦ Independent Periphery JTAG
♦ Configuration Mode Uses IEEE 1149.1 TAP
Controller
♦ Supports Live Insertion/Withdrawal
♦ 3.3V Operation
♦ Industrial Temperature Operation
♦ RoHS-Compliant Packaging
Ordering Information
PART
DS26900N+
TEMP RANGE
-40°C to +85°C
+Denotes a lead-free package.
PIN-PACKAGE
144 LQFP
_____________________________________________ Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known
as errata. Multiple revisions of any device may be simultaneously available through various sales
channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing,
delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit
Maxim’s website at www.maxim-ic.com.
1 page  
__________________________________________________________________________________________DS26900
List of Tables
Table 2-1. Pin Descriptions (Sorted by Function)........................................................................................................ 7
Table 2-2. Pin Description (Sorted by Pin Number) .................................................................................................. 13
Table 4-1. Mode Pins................................................................................................................................................. 20
Table 4-2. Master Arbitration ..................................................................................................................................... 23
Table 4-3. ACT Output States.................................................................................................................................... 24
Table 6-1. Switch TAP Instruction Codes.................................................................................................................. 28
Table 7-1. DS26900 List of Registers........................................................................................................................ 31
Table 7-2. Secondary Port Selection Bits and Indicator Pins.................................................................................... 35
Table 9-1. Periphery JTAG Instruction Codes........................................................................................................... 41
Table 10-1. Thermal Characteristics.......................................................................................................................... 43
Table 10-2. Recommended DC Operating Conditions .............................................................................................. 43
Table 10-3. DC Electrical Characteristics.................................................................................................................. 43
Table 11-1. Switch TAP Controller Interface Timing ................................................................................................. 44
Table 11-2. Master/Slave Port Timing ....................................................................................................................... 45
Table 11-3. Periphery JTAG Interface Timing ........................................................................................................... 46
5
5 Page 
__________________________________________________________________________________________DS26900
NAME
SSPI4
SSPI3
SSPI2
SSPI1
SSPI0
PIN TYPE
FUNCTION
Selected Secondary Port Indicator Bit 4 (Active Low). Along with pins SSPI3,
8 O SSPI2, SSPI1, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See Table 7-2 for more information.
Selected Secondary Port Indicator Bit 3 (Active Low). Along with pins SSPI4,
9 O SSPI2, SSPI1, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See Table 7-2 for more information.
Selected Secondary Port Indicator Bit 2 (Active Low). Along with pins SSPI4,
10 O SSPI3, SSPI1, and SSPI0, this provides a hardware indication of the selected
secondary port. See Table 7-2 for more information.
Selected Secondary Port Indicator Bit 1 (Active Low). Along with pins SSPI4,
11 O SSPI3, SSPI2, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See Table 7-2 for more information.
Selected Secondary Port Indicator Bit 0 (Active Low). Along with pins SSPI4,
12 O SSPI3, SSPI2, and SSPI1, this pin provides a hardware indication of the selected
secondary port. See Table 7-2 for more information.
General-Purpose Input/Output Bit 3. (Internal 20kΩ Pulldown) This pin is a general-
GPIO[3] 14 Ipd/O purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
GPIO[2]
15
Ipd/O
General-Purpose Input/Output Bit 2. (Internal 20kΩ Pulldown) This pin is a general-
purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
General-Purpose Input/Output Bit 1. (Internal 20kΩ Pulldown) This pin is a general-
GPIO[1] 16 Ipd/O purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
General-Purpose Input/Output Bit 0. (Internal 20kΩ Pulldown) This pin is a general-
GPIO[0] 17 Ipd/O purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
Global Reset (Active Low). (Internal 10kΩ Pullup) A low state on this pin provides
RST 33 Ipu an asynchronous reset for global registers and logic. RST should be tied high for
normal operation.
TEST
62
Ipu
Test Enable (Active Low). (Internal 10kΩ Pullup) Factory test input. TEST must be
tied high or unconnected for normal operation.
Output High-Impedance Enable (Active Low). When this pin is asserted low,
HIZ
143
I
internal pullup and pulldown resistors are disabled, all outputs are put into high-
impedance mode, and master request inputs (EREQ, TMREQ1, TMREQ2) are
disabled. PTRST must also be asserted logic 0.
M[1]
141
Ipd
Mode Select Bit 1. (Internal 20kΩ Pulldown) Selects mode of operation of the device
(Single-Package, Cascade-Master, Cascade-Extension, or Deselect.
M[0]
142
Ipd
Mode Select Bit 0. (Internal 20kΩ Pulldown) Selects mode of operation of the device
(Single-Package, Cascade-Master, Cascade-Extension, or Deselect).
Master Conflict Indicator (Active Low). Indicates that more than one device is
MCI
34
requesting to be master.
O Asserted low when more than one of the EREQ, TMREQ1, or TMREQ2 signals is
asserted low.
DPDV
96
O Deselected Port Data Value. This pin directly indicates the state of the DPDV bit in
the Device Configuration Register (DCR).
PTCK
40
I
Periphery JTAG Chain Test Clock. This input must be driven to a logic level during
normal operation.
PTDI
39
I
Periphery JTAG Chain Serial Data Input. This input must be driven to a logic level
during normal operation.
PTDO
38
O Periphery JTAG Chain Serial Data Out
11
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| PDF Descargar | [ Datasheet DS26900.PDF ] | |
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