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PDF DS26324 Data sheet ( Hoja de datos )
| Número de pieza | DS26324 | |
| Descripción | E1/T1/J1 Short-Haul Line Interface Unit | |
| Fabricantes | Dallas Semiconductor | |
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DS26324
3.3V, 16-Channel, E1/T1/J1
Short-Haul Line Interface Unit
GENERAL DESCRIPTION
The DS26324 is a 16-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
impedance matching. A single bill of material can
support E1/T1/J1 that requires no external
termination. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered. The device is offered in a 256-pin
TE-CSBGA, the smallest package available for a
16-channel LIU.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
JTAG
SOFTWARE CONTROL
AND JTAG
LOSS
RTIP
RRING
TTIP
TRING
RECEIVER
TRANSMITTER
1
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
16
FEATURES
16 E1, T1, or J1 Short-Haul Line Interface
Units
Independent E1, T1 or J1 Selections
Fully Internal Impedance Match Requires No
External Resistors
Software-Selectable Transmit and Receive-
Side Impedance Match
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss of Signal Detection as
per T1.231, G.775 and ETS 300 233
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock Will Be Internally
Adapted for T1 or E1 Usage
Receiver Signal Level Indicator from -2.5dB to
-20dB in 2.5dB Increments
Two Built-In BERT Testers for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Receive Monitor Mode Handles Combinations
of 14dB to 20dB of Resistive Attenuation
Along with 12dB to 30dB of Cable Attenuation
Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
G.775, G.823, ETS 300 166, and ETS 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as Per IEEE 1149.1
ORDERING INFORMATION
PART
DS26324G
DS26324GN
TEMP RANGE PIN-PACKAGE
0°C to +70°C 256 TE-CSBGA
-40°C to +85°C 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 053107
1 page  
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
LIST OF TABLES
Table 4-1. Pin Descriptions........................................................................................................................................ 10
Table 5-1. Parallel Port Mode Selection and Pin Functions ...................................................................................... 18
Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters ............................................ 21
Table 5-3. Registers Related to Control of DS26324 Transmitters ........................................................................... 21
Table 5-4. Template Selections for Short-Haul Mode ............................................................................................... 22
Table 5-6. LIU Front-End Values ............................................................................................................................... 26
Table 5-7. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications ............................................ 28
Table 5-8. AIS Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications.............................................. 29
Table 5-9. AIS Detection and Reset Criteria for DS26324 ........................................................................................ 29
Table 5-10. Registers Related to AIS Detection........................................................................................................ 29
Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting ................................................................... 30
Table 5-12. Pseudorandom Pattern Generation........................................................................................................ 35
Table 5-13. Repetitive Pattern Generation ................................................................................................................ 35
Table 6-1. Primary Register Set ................................................................................................................................ 40
Table 6-2. Secondary Register Set............................................................................................................................ 41
Table 6-3. Individual LIU Register Set....................................................................................................................... 42
Table 6-4. BERT Register Set ................................................................................................................................... 43
Table 6-5. Primary Register Set Bit Map ................................................................................................................... 44
Table 6-6. Secondary Register Set Bit Map .............................................................................................................. 45
Table 6-7. Individual LIU Register Set Bit Map.......................................................................................................... 46
Table 6-8. BERT Register Bit Map ............................................................................................................................ 47
Table 6-9. G.772 Monitoring Control (LIU 1) ............................................................................................................. 54
Table 6-10. G.772 Monitoring Control (LIU 9) ........................................................................................................... 54
Table 6-11. TST Template Select Transmitter Register (LIUs 1–8) .......................................................................... 59
Table 6-12. TST Template Select Transmitter Register (LIUs 9–16) ........................................................................ 59
Table 6-13. Template Selection................................................................................................................................. 60
Table 6-14. Address Pointer Bank Selection............................................................................................................. 63
Table 6-15. DS26324 MCLK Selections.................................................................................................................... 69
Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection ................................................................................ 73
Table 6-17. Receiver Signal Level............................................................................................................................. 75
Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8 .............................................................................. 79
Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16 ............................................................................ 79
Table 6-20. PLL Clock Select .................................................................................................................................... 82
Table 6-21. Clock A Select ........................................................................................................................................ 82
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 95
Table 7-2. ID Code Structure..................................................................................................................................... 96
Table 7-3. Device ID Codes....................................................................................................................................... 96
Table 8-1. Recommended DC Operating Conditions ................................................................................................ 97
Table 8-2. Pin Capacitance ....................................................................................................................................... 97
Table 8-3. DC Characteristics.................................................................................................................................... 97
Table 9-1. Transmitter Characteristics....................................................................................................................... 98
Table 9-2. Receiver Characteristics........................................................................................................................... 98
Table 9-3. Intel Read Mode Characteristics .............................................................................................................. 99
Table 9-4. Intel Write Cycle Characteristics ............................................................................................................ 102
Table 9-5. Motorola Read Cycle Characteristics ..................................................................................................... 105
Table 9-6. Motorola Write Cycle Characteristics ..................................................................................................... 108
Table 9-7. Serial Port Timing Characteristics .......................................................................................................... 111
Table 9-8. Transmitter System Timing..................................................................................................................... 112
Table 9-9. Receiver System Timing......................................................................................................................... 113
Table 9-10. JTAG Timing Characteristics................................................................................................................ 114
Table 12-1. Thermal Characteristics........................................................................................................................ 117
Table 12-2. Package Power Dissipation (for Thermal Considerations)................................................................... 117
Table 12-3. Per-Channel Power-Down Savings (for Thermal Considerations)....................................................... 118
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5 Page 
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
NAME
PIN TYPE
FUNCTION
RESREF
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
RRING8
RRING9
RRING10
RRING11
RRING12
RRING13
RRING14
RRING15
RRING16
R9
Analog
input
Resistor Reference. If fully internal receive impedance match is
selected, a 16kΩ ±1% resistor to GND is needed. If not used, tie pin
low.
A2
C2
H2
N2
R1
R3
R8
R13
T15
Analog
input
Receive Bipolar Ring for Channels 1–16. Receive analog input for
differential receiver. Data and clock are recovered and output at
RPOS/RNEG and RCLK pins, respectively. The differential inputs of
RTIPn and RRINGn can provide internal impedance matching with
P15 external resistance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.
J15
D15
B16
B14
B9
B4
DIGITAL Tx/Rx
TPOS1/TDATA1
TPOS2/TDATA2
TPOS3/TDATA3
TPOS4/TDATA4
TPOS5/TDATA5
TPOS6/TDATA6
TPOS7/TDATA7
TPOS8/TDATA8
TPOS9/TDATA9
TPOS10/TDATA10
TPOS11/TDATA11
TPOS12/TDATA12
TPOS13/TDATA13
TPOS14/TDATA14
TPOS15/TDATA15
TPOS16/TDATA16
TNEG1
TNEG2
TNEG3
TNEG4
TNEG5
TNEG6
TNEG7
TNEG8
TNEG9
TNEG10
TNEG11
TNEG12
TNEG13
TNEG14
TNEG15
TNEG16
F6
G7
J6
K6
L9
N5
P12
M11
L11
J11
G11
C14
F9
E7
N12
D5
C3
J14
J5
G10
M6
P6
P7
K9
L12
J12
H11
E13
G8
F7
C6
C5
Transmit Positive Data Input for Channels 1–6. When DS26324 is
configured in dual-rail mode, the data input to TPOSn is output as a
positive pulse on the line (tip and ring).
I Transmit Data Input for Channels 1–16. When the device is
configured in single-rail mode NRZ data is input to TDATAn. The data
is sampled on the falling edge of TCLKn and encoded HDB3/B8ZS or
AMI before being output to the line.
Transmit Negative Data for Channels 1–16. When DS26324 is
configured in dual-rail mode. The data input to TNEGn is output as a
negative mark on the line. TPOS and TNEG in dual-rail mode result in
positive and negative pulses sent on the line:
TPOSn
I0
0
1
1
TNEGn
0
1
0
1
OUTPUT PULSE
Space
Negative mark
Positive mark
Space
11 of 120
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS26324.PDF ] | |
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