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PDF 25AA128 Data sheet ( Hoja de datos )
| Número de pieza | 25AA128 | |
| Descripción | 128K SPI Bus Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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25AA128/25LC128
128K SPI Bus Serial EEPROM
Device Selection Table
Part Number
25LC128
25AA128
VCC Range
2.5-5.5V
1.8-5.5V
Page Size
64 Byte
64 Byte
Features
• Max. Clock 10 MHz
• Low-power CMOS Technology
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 μA at 5.5V
• 16,384 x 8-bit Organization
• 64 Byte Page
• Self-timed Erase and Write Cycles (5 ms max.)
• Block Write Protection
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Ranges Supported;
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
• Standard and Pb-free Packages Available
Pin Function Table
Name
Function
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Temp. Ranges
I,E
I
Packages
P, SN, ST, MF
P, SN, ST, MF
Description
The Microchip Technology Inc. 25AA128/25LC128
(25XX128*) are 128k-bit Serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface (SPI) compatible serial bus. The
bus signals required are a clock input (SCK) plus sep-
arate data in (SI) and data out (SO) lines. Access to the
device is controlled through a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25XX128 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead DFN and 8-lead TSSOP.
Pb-free (Pure Sn) finish is also available.
Package Types (not to scale)
TSSOP
(ST)
PDIP/SOIC
(P, SN)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6
5
SCK
SI
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
DFN
(MF)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
* 25XX128 is used in this document as a generic part number for the 25AA128, 25LC128 devices.
© 2007 Microchip Technology Inc.
DS21831C-page 1
1 page  
25AA128/25LC128
FIGURE 1-1: HOLD TIMING
CS
16
SCK
SO n + 2
n+1
17
18
n
16 17
19
High-Impedance
n
SI
n+2
n+1
n
Don’t Care
5
n
HOLD
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
13
MSB out
Don’t Care
8
14
4
12
11
3
LSB in
3
15
ISB out
Mode 1,1
Mode 0,0
© 2007 Microchip Technology Inc.
DS21831C-page 5
5 Page 
25AA128/25LC128
2.6 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3: ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
00
none
01
upper 1/4
(3000h-3FFFh)
10
upper 1/2
(2000h-3FFFh)
11
all
(0000h-3FFFh)
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Data to STATUS Register
0 00 00 0 01 7 6 54 3 2 10
High-Impedance
SO
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
© 2007 Microchip Technology Inc.
DS21831C-page 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 25AA128.PDF ] | |
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